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/linux/Documentation/devicetree/bindings/nvmem/
H A Drockchip,otp.yaml4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3528-otp
18 - rockchip,rk3562-otp
19 - rockchip,rk3568-otp
20 - rockchip,rk3576-otp
21 - rockchip,rk3588-otp
59 - rockchip,px30-otp
[all …]
H A Dnintendo-otp.yaml4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
14 See https://wiiubrew.org/wiki/Hardware/OTP
25 - nintendo,hollywood-otp
26 - nintendo,latte-otp
39 otp@d8001ec {
40 compatible = "nintendo,latte-otp";
H A Dlpc1850-otp.txt1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
H A Dst,stm32-romem.yaml11 flash, OTP, read-only HW regs... This contains various information such as:
25 - st,stm32f4-otp
40 st,non-secure-otp:
58 compatible = "st,stm32f4-otp";
69 st,non-secure-otp;
H A Dsunplus,sp7021-ocotp.yaml8 title: On-Chip OTP Memory for Sunplus SP7021
58 otp: otp@9c00af00 {
/linux/drivers/nvmem/
H A Dsunplus-ocotp.c20 * OTP memory
77 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) in sp_otp_read_real() argument
93 writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & in sp_otp_read_real()
94 OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); in sp_otp_read_real()
95 writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); in sp_otp_read_real()
96 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, in sp_otp_read_real()
97 otp->base[OTPRX] + OTP_CONTROL_2); in sp_otp_read_real()
98 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) & SEL_BAK_KEY2_MASK & SW_TRIM_EN_MASK in sp_otp_read_real()
100 otp->base[OTPRX] + OTP_CONTROL_2); in sp_otp_read_real()
101 writel((readl(otp->base[OTPRX] + OTP_CONTROL_2) & OTP_RD_PERIOD_MASK) | CPU_CLOCK, in sp_otp_read_real()
[all …]
H A Dmxs-ocotp.c3 * Freescale MXS On-Chip OTP driver
37 static int mxs_ocotp_wait(struct mxs_ocotp *otp) in mxs_ocotp_wait() argument
43 status = readl(otp->base); in mxs_ocotp_wait()
62 struct mxs_ocotp *otp = context; in mxs_ocotp_read() local
66 ret = clk_enable(otp->clk); in mxs_ocotp_read()
70 writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()
72 ret = mxs_ocotp_wait(otp); in mxs_ocotp_read()
77 writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET); in mxs_ocotp_read()
82 ret = mxs_ocotp_wait(otp); in mxs_ocotp_read()
91 *buf++ = readl(otp->base + offset); in mxs_ocotp_read()
[all …]
H A Dnintendo-otp.c3 * Nintendo Wii and Wii U OTP driver
5 * This is a driver exposing the OTP of a Nintendo Wii or Wii U console.
10 * Based on reversed documentation from https://wiiubrew.org/wiki/Hardware/OTP
38 .name = "wii-otp",
43 .name = "wiiu-otp",
67 { .compatible = "nintendo,hollywood-otp", .data = &hollywood_otp_data },
68 { .compatible = "nintendo,latte-otp", .data = &latte_otp_data },
113 .name = "nintendo-otp",
119 MODULE_DESCRIPTION("Nintendo Wii and Wii U OTP driver");
H A Dstm32-romem.c56 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result) in stm32_bsec_smc() argument
61 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); in stm32_bsec_smc()
92 u32 otp = i >> 2; in stm32_bsec_read() local
94 if (otp < priv->lower) { in stm32_bsec_read()
99 ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0, in stm32_bsec_read()
102 dev_err(dev, "Can't read data%d (%d)\n", otp, in stm32_bsec_read()
253 * STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
273 * STM32MP25 BSEC OTP: 3 regions of 32-bits data words
274 * lower OTP (OTP0 to OTP127), bitwise (1-bit) programmable
275 * mid OTP (OTP128 to OTP255), bulk (32-bit) programmable
[all …]
H A Dimx-ocotp.c29 * OTP Bank0 Word0
32 * of two consecutive OTP words.
249 * ipg_clk. OTP writes will work at maximum bus frequencies as long in imx_ocotp_set_imx6_timing()
252 * Note: there are minimum timings required to ensure an OTP fuse burns in imx_ocotp_set_imx6_timing()
261 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before in imx_ocotp_set_imx6_timing()
271 * value will mess up a re-load of the shadow registers post OTP in imx_ocotp_set_imx6_timing()
324 /* allow only writing one complete OTP word at a time */ in imx_ocotp_write()
362 * In banked/i.MX7 mode the OTP register bank goes into waddr in imx_ocotp_write()
372 * OTP write/read address specifies one of 128 word address in imx_ocotp_write()
388 * protect programming same OTP bit twice, before program OCOTP will in imx_ocotp_write()
[all …]
H A Dstm32-bsec-optee-ta.c13 * Read OTP memory
15 * [in] value[0].a OTP start offset in byte
18 * [out] memref[1].size Size of OTP to be read
23 * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller
28 * Write OTP memory
30 * [in] value[0].a OTP start offset in byte
33 * [in] memref[1].size Size of OTP to be written
38 * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller
H A Drcar-efuse.c3 * Renesas R-Car E-FUSE/OTP Driver
125 { .compatible = "renesas,r8a779g0-otp", .data = &rcar_fuse_v4h },
126 { .compatible = "renesas,r8a779h0-otp", .data = &rcar_fuse_v4m },
140 MODULE_DESCRIPTION("Renesas R-Car E-FUSE/OTP driver");
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Deeprom.c51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
109 if (!np || !of_property_read_bool(np, "mediatek,eeprom-merge-otp")) in mt7603_apply_cal_free_data()
166 if (dev->mt76.otp.data) { in mt7603_eeprom_init()
168 mt7603_apply_cal_free_data(dev, dev->mt76.otp.data); in mt7603_eeprom_init()
170 memcpy(dev->mt76.eeprom.data, dev->mt76.otp.data, in mt7603_eeprom_init()
/linux/include/linux/mfd/wm831x/
H A Dotp.h3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
73 * R30728 (0x7808) - Factory OTP ID
84 * R30729 (0x7809) - Factory OTP 1
97 * R30730 (0x780A) - Factory OTP 2
104 * R30731 (0x780B) - Factory OTP 3
117 * R30732 (0x780C) - Factory OTP 4
128 * R30733 (0x780D) - Factory OTP 5
135 * R30736 (0x7810) - Customer OTP ID
/linux/drivers/mtd/nand/onenand/
H A DKconfig45 bool "OneNAND OTP Support"
49 Also, 1st Block of NAND Flash Array can be used as OTP.
51 The OTP block can be read, programmed and locked using the same
53 OTP block cannot be erased.
55 OTP block is fully-guaranteed to be a valid block.
H A Donenand_base.c15 * OTP support
50 /* Default OneNAND/Flex-OneNAND OTP options*/
51 static int otp; variable
53 module_param(otp, int, 0400);
54 MODULE_PARM_DESC(otp, "Corresponding behaviour of OneNAND in OTP"
55 "Syntax : otp=LOCK_TYPE"
56 "LOCK_TYPE : Keys issued, for specific OTP Lock type"
58 " : 1 -> OTP Block lock"
60 " : 3 -> BOTH OTP Block and 1st Block lock");
1909 /* Exclude 1st OTP and OTP blocks for cache program feature */ in onenand_write_ops_nolock()
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/dvm/
H A Deeprom.c716 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); in iwl_eeprom_verify_signature()
723 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", in iwl_eeprom_verify_signature()
724 nvm_is_otp ? "OTP" : "EEPROM", gp); in iwl_eeprom_verify_signature()
731 * OTP related functions
747 /* OTP only valid for CP/PP and after */ in iwl_nvm_is_otp()
781 * this is only applicable for HW with OTP shadow RAM in iwl_init_otp_access()
803 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); in iwl_read_otp_word()
811 /* set the uncorrectable OTP ECC bit for acknowledgment */ in iwl_read_otp_word()
814 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); in iwl_read_otp_word()
819 /* set the correctable OTP ECC bit for acknowledgment */ in iwl_read_otp_word()
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dpcie.c359 struct brcmf_otp_params otp; member
1957 brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n", in brcmf_pcie_parse_otp_sys_vendor()
1980 strscpy(devinfo->otp.module, p, len + 1); in brcmf_pcie_parse_otp_sys_vendor()
1983 strscpy(devinfo->otp.vendor, p, len + 1); in brcmf_pcie_parse_otp_sys_vendor()
1986 strscpy(devinfo->otp.version, p, len + 1); in brcmf_pcie_parse_otp_sys_vendor()
1994 brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n", in brcmf_pcie_parse_otp_sys_vendor()
1995 devinfo->otp.module, devinfo->otp.vendor, in brcmf_pcie_parse_otp_sys_vendor()
1996 devinfo->otp.version); in brcmf_pcie_parse_otp_sys_vendor()
1998 if (!devinfo->otp.module[0] || in brcmf_pcie_parse_otp_sys_vendor()
1999 !devinfo->otp.vendor[0] || in brcmf_pcie_parse_otp_sys_vendor()
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-agn-hw.h51 #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
52 #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
53 #define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */
54 #define OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */
/linux/Documentation/devicetree/bindings/regulator/
H A Dpalmas-pmic.txt3 The tps659038 for the AM57x class have OTP spins that
5 is not a need to add the OTP spins to the palmas driver. The
35 For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
50 ti,smps-range - OTP has the wrong range set for the hardware so override
/linux/include/linux/ssb/
H A Dssb_driver_chipcommon.h47 #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
61 #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
67 #define SSB_CHIPCO_OTPC 0x0014 /* OTP control */
74 #define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */
398 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
399 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
400 #define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
401 #define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
548 /** OTP **/
550 /* OTP regions */
[all …]
/linux/include/uapi/mtd/
H A Dmtd-abi.h170 /* OTP mode selection */
227 /* Set OTP (One-Time Programmable) mode (factory vs. user) */
229 /* Get number of OTP (One-Time Programmable) regions */
231 /* Get all OTP (One-Time Programmable) info about MTD */
315 * @MTD_FILE_MODE_NORMAL: OTP disabled, ECC enabled
316 * @MTD_FILE_MODE_OTP_FACTORY: OTP enabled in factory mode
317 * @MTD_FILE_MODE_OTP_USER: OTP enabled in user mode
318 * @MTD_FILE_MODE_RAW: OTP disabled, ECC disabled
/linux/drivers/mtd/nand/raw/
H A Dnand_macronix.c82 /* RANDEN and RANDOPT OTP bits are programmed */ in macronix_nand_randomizer_check_enable()
113 rand_otp = of_property_read_bool(dn, "mxic,enable-randomizer-otp"); in macronix_nand_onfi_init()
336 /* Always report that OTP is unlocked. Reason is that this in macronix_30lfxg18ac_get_otp_info()
337 * type of flash chip doesn't provide way to check that OTP in macronix_30lfxg18ac_get_otp_info()
339 * volatile register. Technically OTP region could be locked in macronix_30lfxg18ac_get_otp_info()
342 * always returns -EOPNOTSUPP) and thus we report that OTP in macronix_30lfxg18ac_get_otp_info()
421 dev_err(&mtd->dev, "failed to perform OTP IO: %i\n", ret); in __macronix_30lfxg18ac_rw_otp()
425 dev_err(&mtd->dev, "failed to leave OTP mode after %s\n", in __macronix_30lfxg18ac_rw_otp()
/linux/drivers/mfd/
H A Dwm831x-otp.c3 * wm831x-otp.c -- OTP for Wolfson WM831x PMICs
19 #include <linux/mfd/wm831x/otp.h>
/linux/drivers/misc/mchp_pci1xxxx/
H A DKconfig2 tristate "Microchip PCI1XXXX PCIe to GPIO Expander + OTP/EEPROM manager"
11 which also has registers to interface with the OTP and EEPROM.

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