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/linux/drivers/nvmem/
H A Drockchip-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip OTP Driver
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
15 #include <linux/nvmem-provider.h>
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
41 #define OTPC_SBPI_DONE BIT(1)
63 #define RK3588_BURST_NUM 1
67 #define RK3588_RD_DONE BIT(1)
85 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
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H A Dlan9662-otpc.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/nvmem-provider.h>
18 #define OTP_OTP_FUNC_CMD_OTP_PROGRAM BIT(1)
27 #define OTP_OTP_STATUS_OTP_CPUMPEN BIT(1)
47 static int lan9662_otp_power(struct lan9662_otp *otp, bool up) in lan9662_otp_power() argument
49 void __iomem *pwrdn = OTP_OTP_PWR_DN(otp->base); in lan9662_otp_power()
53 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_power()
55 return -ETIMEDOUT; in lan9662_otp_power()
63 static int lan9662_otp_execute(struct lan9662_otp *otp) in lan9662_otp_execute() argument
65 if (lan9662_otp_wait_flag_clear(OTP_OTP_CMD_GO(otp->base), in lan9662_otp_execute()
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H A Dsunplus-ocotp.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-provider.h>
21 * OTP memory
48 #define OTP_LOAD_SECURE_DATA BIT(1)
49 #define OTP_LOAD_SECURE_DATA_MASK ~BIT(1)
78 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) in sp_otp_read_real() argument
94 writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & in sp_otp_read_real()
95 OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); in sp_otp_read_real()
96 writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); in sp_otp_read_real()
97 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, in sp_otp_read_real()
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H A Dmxs-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale MXS On-Chip OTP driver
15 #include <linux/nvmem-provider.h>
37 static int mxs_ocotp_wait(struct mxs_ocotp *otp) in mxs_ocotp_wait() argument
42 while (timeout--) { in mxs_ocotp_wait()
43 status = readl(otp->base); in mxs_ocotp_wait()
52 return -EBUSY; in mxs_ocotp_wait()
54 return -EIO; in mxs_ocotp_wait()
62 struct mxs_ocotp *otp = context; in mxs_ocotp_read() local
66 ret = clk_enable(otp->clk); in mxs_ocotp_read()
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H A Dstm32-romem.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Factory-programmed memory read access driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
9 #include <linux/arm-smccc.h>
12 #include <linux/nvmem-provider.h>
18 #include "stm32-bsec-optee-ta.h"
20 /* BSEC secure service access from non-secure */
51 *buf8++ = readb_relaxed(priv->base + i); in stm32_romem_read()
56 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result) in stm32_bsec_smc() argument
61 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); in stm32_bsec_smc()
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H A Dnintendo-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Nintendo Wii and Wii U OTP driver
5 * This is a driver exposing the OTP of a Nintendo Wii or Wii U console.
7 * This memory contains common and per-console keys, signatures and
10 * Based on reversed documentation from https://wiiubrew.org/wiki/Hardware/OTP
19 #include <linux/nvmem-provider.h>
39 .name = "wii-otp",
40 .num_banks = 1,
44 .name = "wiiu-otp",
56 while (words--) { in nintendo_otp_reg_read()
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H A Dimx-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
21 #include <linux/nvmem-provider.h>
29 * OTP Bank0 Word0
32 * of two consecutive OTP words.
107 void __iomem *base = priv->base; in imx_ocotp_wait_for_busy()
109 bm_ctrl_busy = priv->params->ctrl.bm_busy; in imx_ocotp_wait_for_busy()
110 bm_ctrl_error = priv->params->ctrl.bm_error; in imx_ocotp_wait_for_busy()
114 for (count = 10000; count >= 0; count--) { in imx_ocotp_wait_for_busy()
124 * - A write is performed to a shadow register during a shadow in imx_ocotp_wait_for_busy()
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H A Dstm32-bsec-optee-ta.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OP-TEE STM32MP BSEC PTA interface, used by STM32 ROMEM driver
5 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
10 #include "stm32-bsec-optee-ta.h"
13 * Read OTP memory
15 * [in] value[0].a OTP start offset in byte
16 * [in] value[0].b Access type (0:shadow, 1:fuse, 2:lock)
17 * [out] memref[1].buffer Output buffer to store read values
18 * [out] memref[1].size Size of OTP to be read
21 * TEE_SUCCESS - Invoke command success
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H A Drcar-efuse.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Renesas R-Car E-FUSE/OTP Driver
12 #include <linux/nvmem-provider.h>
25 unsigned int bank; /* 0: PFC + E-FUSE, 1: OPT_MEM + E-FUSE */
36 ret = pm_runtime_resume_and_get(fuse->dev); in rcar_fuse_reg_read()
40 __ioread32_copy(val, fuse->base + offset, bytes / 4); in rcar_fuse_reg_read()
42 pm_runtime_put(fuse->dev); in rcar_fuse_reg_read()
49 struct device *dev = &pdev->dev; in rcar_fuse_probe()
53 .name = "rcar-fuse", in rcar_fuse_probe()
73 return -ENOMEM; in rcar_fuse_probe()
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/linux/Documentation/devicetree/bindings/nvmem/
H A Drockchip,otp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3576-otp
18 - rockchip,rk3588-otp
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H A Dlpc1850-otp.txt1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
7 - reg: Must contain an entry with the physical base address and length
8 for each entry in reg-names.
9 - address-cells: must be set to 1.
10 - size-cells: must be set to 1.
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
18 #address-cells = <1>;
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H A Dnintendo-otp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
11 which contains common and per-console keys, signatures and related data
14 See https://wiiubrew.org/wiki/Hardware/OTP
17 - Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
20 - $ref: nvmem.yaml#
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H A Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
20 - $ref: nvmem-deprecated-cells.yaml#
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H A Dmicrochip,lan9662-otpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,lan9662-otpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN9662 OTP Controller (OTPC)
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 OTP controller drives a NVMEM memory where system specific data
18 - $ref: nvmem.yaml#
23 - items:
24 - const: microchip,lan9668-otpc
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H A Dsunplus,sp7021-ocotp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/nvmem/sunplus,sp7021-ocotp.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: On-Chip OTP Memory for Sunplus SP7021
11 - Vincent Shih <vincent.sunplus@gmail.com>
14 - $ref: nvmem.yaml#
15 - $ref: nvmem-deprecated-cells.yaml#
19 const: sunplus,sp7021-ocotp
24 reg-names:
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/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
21 User-defined MTD device name. Can be used to assign user friendly
26 '#address-cells':
29 '#size-cells':
36 - compatible
39 "@[0-9a-f]+$":
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/linux/include/linux/mfd/wm831x/
H A Dotp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
17 * R30720 (0x7800) - Unique ID 1
19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
24 * R30721 (0x7801) - Unique ID 2
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
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/linux/drivers/crypto/
H A Datmel-sha204a.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "atmel-i2c.h"
24 struct atmel_i2c_client_priv *i2c_priv = work_data->ctx; in atmel_sha204a_rng_done()
28 dev_warn_ratelimited(&i2c_priv->client->dev, in atmel_sha204a_rng_done()
32 rng->priv = (unsigned long)work_data; in atmel_sha204a_rng_done()
33 atomic_dec(&i2c_priv->tfm_count); in atmel_sha204a_rng_done()
44 /* keep maximum 1 asynchronous read in flight at any time */ in atmel_sha204a_rng_read_nonblocking()
45 if (!atomic_add_unless(&i2c_priv->tfm_count, 1, 1)) in atmel_sha204a_rng_read_nonblocking()
48 if (rng->priv) { in atmel_sha204a_rng_read_nonblocking()
49 work_data = (struct atmel_i2c_work_data *)rng->priv; in atmel_sha204a_rng_read_nonblocking()
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/linux/drivers/mtd/nand/onenand/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 from 1 to 0. There is a rare possibility that even though the
45 bool "OneNAND OTP Support"
48 a One-Time Programmable Block memory area.
49 Also, 1st Block of NAND Flash Array can be used as OTP.
51 The OTP block can be read, programmed and locked using the same
53 OTP block cannot be erased.
55 OTP block is fully-guaranteed to be a valid block.
61 Since the device is equipped with two DataRAMs, and two-plane NAND
/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dpcie.c1 // SPDX-License-Identifier: ISC
52 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie");
53 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie");
54 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie");
55 BRCMF_FW_CLM_DEF(4355, "brcmfmac4355-pcie");
56 BRCMF_FW_CLM_DEF(4355C1, "brcmfmac4355c1-pcie");
57 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie");
58 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie");
59 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie");
60 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie");
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/linux/include/linux/ssb/
H A Dssb_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
47 #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
61 #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
67 #define SSB_CHIPCO_OTPC 0x0014 /* OTP control */
74 #define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */
117 #define SSB_CHIPCO_JCTL_EN 1 /* Enable Jtag master */
160 #define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
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/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-agn-hw.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014 Intel Corporation
6 * Please use this file (iwl-agn-hw.h) only for hardware-related definitions.
18 #define IWLAGN_RTC_INST_SIZE (IWLAGN_RTC_INST_UPPER_BOUND - \
20 #define IWLAGN_RTC_DATA_SIZE (IWLAGN_RTC_DATA_UPPER_BOUND - \
28 (IWL60_RTC_INST_UPPER_BOUND - IWL60_RTC_INST_LOWER_BOUND)
30 (IWL60_RTC_DATA_UPPER_BOUND - IWL60_RTC_DATA_LOWER_BOUND)
42 #define IWLAGN_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm: 1 milliwatt */
51 #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
52 #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
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/linux/Documentation/devicetree/bindings/regulator/
H A Dpalmas-pmic.txt3 The tps659038 for the AM57x class have OTP spins that
5 is not a need to add the OTP spins to the palmas driver. The
11 - compatible : Should be from the list
12 ti,twl6035-pmic
13 ti,twl6036-pmic
14 ti,twl6037-pmic
15 ti,tps65913-pmic
16 ti,tps65914-pmic
17 ti,tps65917-pmic
18 ti,tps659038-pmic
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/linux/drivers/mtd/nand/raw/
H A Dnand_macronix.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
21 #define MACRONIX_RANDOMIZER_BIT BIT(1)
23 #define MACRONIX_RANDOMIZER_RANDEN BIT(1)
54 if (!chip->parameters.supports_set_get_features || in macronix_nand_setup_read_retry()
56 chip->parameters.set_feature_list)) in macronix_nand_setup_read_retry()
57 return -ENOTSUPP; in macronix_nand_setup_read_retry()
82 /* RANDEN and RANDOPT OTP bits are programmed */ in macronix_nand_randomizer_check_enable()
84 ret = nand_prog_page_op(chip, 0, 0, feature, 1); in macronix_nand_randomizer_check_enable()
104 struct nand_parameters *p = &chip->parameters; in macronix_nand_onfi_init()
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/linux/include/uapi/mtd/
H A Dmtd-abi.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> et al.
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
55 * @MTD_OPS_RAW: data are transferred as-is, with no error correction;
64 MTD_OPS_AUTO_OOB = 1,
69 * struct mtd_write_req - data structure for requesting a write operation
74 * @usr_data: user-provided data buffer
75 * @usr_oob: user-provided OOB buffer
80 * writes in various modes. To write to OOB-only, set @usr_data == NULL, and to
81 * write data-only, set @usr_oob == NULL. However, setting both @usr_data and
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