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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-inno-usb2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
19 - rockchip,rk3328-usb2phy
[all …]
H A Drockchip,inno-usb2phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchi
[all...]
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
[all...]
H A Dphy-stm32-usbphyc.txt3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
14 |_ PHY port#2 ----| |________________
16 |_ UTMI switch_______| OTG controller
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
26 - #address-cells: number of address cells for phys sub-nodes, must be <1>
27 - #size-cells: number of size cells for phys sub-nodes, must be <0>
[all …]
H A Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
27 "port" is typically used to denote the physical USB receptacle. The device
28 tree binding in this document uses the term "port" to refer to the logical
[all …]
H A Dallwinner,sun8i-h3-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-h3-usb-phy
20 - allwinner,sun50i-h616-usb-phy
24 - description: PHY Control registers
[all …]
H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
13 selects either OTG or HOST controller for the second PHY port. It also sets
19 |_ PHY port#1 _________________ HOST controller
22 |_ PHY port#2 ----| |________________
24 |_ UTMI switch_______| OTG controller
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dste-dma40.txt4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
19 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
[all …]
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsso
[all...]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dcdns,usb3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
[all …]
H A Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare HS OTG USB 2.0 controller
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
[all …]
H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
23 connected to the Glue to serve as OTG ID change detection.
26 host-only mode.
33 - amlogic,meson-gxl-usb-ctrl
[all …]
H A Dfsl-usb.txt9 - compatible : Should be "fsl-usb2-mph" for multi port host USB
10 controllers, or "fsl-usb2-dr" for dual role USB controllers
11 or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121.
13 also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132).
14 - phy_type : For multi port host USB controllers, should be one of
17 - reg : Offset and length of the register set for the device
18 - port0 : boolean; if defined, indicates port0 is connected for
19 fsl-usb2-mph compatible controllers. Either this property or
20 "port1" (or both) must be defined for "fsl-usb2-mph" compatible
22 - port1 : boolean; if defined, indicates port1 is connected for
[all …]
H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
17 The DRD controller has a glue layer IPPC (IP Port Control), and its host is
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
[all …]
H A Dmediatek,mtu3.txt4 - compatible : should be "mediatek,<soc-model>-mtu3", "mediatek,mtu3",
5 soc-model is the name of SoC, such as mt8173, mt2712 etc,
8 - "mediatek,mt8173-mtu3"
9 - reg : specifies physical base address and size of the registers
10 - reg-names: should be "mac" for device IP and "ippc" for IP port control
11 - interrupts : interrupt used by the device IP
12 - power-domains : a phandle to USB power domain node to control USB's
14 - vusb33-supply : regulator of USB avdd3.3v
15 - clocks : a list of phandle + clock-specifier pairs, one for each
16 entry in clock-names
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-tiger-haikou.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
8 #include "rk3588-tiger.dtsi"
11 model = "Theobroma Systems RK3588-Q7 SoM on Haikou devkit";
12 compatible = "tsd,rk3588-tiger-haikou", "tsd,rk3588-tiger", "rockchip,rk3588";
20 stdout-path = "serial2:115200n8";
23 dc_12v: dc-12v-regulator {
24 compatible = "regulator-fixed";
25 regulator-name = "dc_12v";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dulcb-kf.dtsi1 // SPDX-License-Identifier: GPL-2.0
18 #clock-cells = <0>;
19 compatible = "gpio-mux-clock";
21 select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>;
24 hdmi1-out {
25 compatible = "hdmi-connector";
28 port {
30 remote-endpoint = <&adv7513_out>;
35 reg_t1p8v: regulator-t1p8v {
36 compatible = "regulator-fixed";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/power/supply/
H A Dbq24190.txt1 TI BQ24190 Li-Ion Battery Charger
4 - compatible: contains one of the following:
9 - reg: integer, I2C address of the charger.
10 - interrupts[-extended]: configuration for charger INT pin.
13 - monitored-battery: phandle of battery characteristics devicetree node
15 + precharge-current-microamp: maximum charge current during precharge
17 + charge-term-current-microamp: a charge cycle terminates when the
21 - ti,system-minimum-microvolt: when power is connected and the battery is below
25 - usb-otg-vbus:
28 either USB host mode or for charging on the OTG port.
[all …]
H A Drichtek,rt9467.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
11 - ChiaEn Wu <chiaen_wu@richtek.com>
14 RT9467 is a switch-mode single cell Li-Ion/Li-Polymer battery charger for
16 MOSFETs, input current sensing and regulation, high-accuracy voltage
20 The RT9467 also features USB On-The-Go (OTG) support. It also integrates
21 D+/D- pin for USB host/charging port detection.
24 https://www.richtek.com/assets/product_file/RT9467/DS9467-01.pdf
[all …]
H A Drichtek,rt9471.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alina Yu <alina_yu@richtek.com>
11 - ChiYuan Huang <cy_huang@richtek.com>
14 RT9471 is a switch-mode single cell Li-Ion/Li-Polymer battery charger for
15 portable applications. It supports USB BC1.2 port detection, current and
19 https://www.richtek.com/assets/product_file/RT9471=RT9471D/DS9471D-02.pdf
28 charge-enable-gpios:
32 wakeup-source: true
[all …]
/freebsd/sys/contrib/device-tree/src/mips/ingenic/
H A Dgcw0.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/clock/ingenic,tcu.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/iio/adc/ingenic,adc.h>
9 #include <dt-bindings/input/input.h>
29 stdout-path = "serial2:57600n8";
33 compatible = "regulator-fixed";
34 regulator-name = "vcc";
36 regulator-min-microvolt = <3300000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-venice-gw72xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
16 compatible = "gpio-usb-b-connector", "usb-b-connector";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_usbcon1>;
20 label = "otg";
21 vbus-supply = <&reg_usb1_vbus>;
22 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
[all …]

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