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Searched full:oscin (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dti,lmk04832.yaml44 - const: oscin
154 lmk04832_oscin: oscin {
159 clock-output-names = "lmk04832-oscin";
180 clock-names = "oscin";
H A Damlogic,c3-peripherals-clkc.yaml48 - const: oscin
104 "oscin",
/linux/drivers/clk/meson/
H A Dc3-peripherals.c69 .fw_name = "oscin",
156 { .fw_name = "oscin" },
402 { .fw_name = "oscin" },
466 { .fw_name = "oscin" },
475 { .fw_name = "oscin" },
538 { .fw_name = "oscin" },
572 { .fw_name = "oscin" },
604 .fw_name = "oscin",
688 { .fw_name = "oscin" },
755 { .fw_name = "oscin" }
[all …]
/linux/arch/arm/mach-davinci/
H A Dclock.h47 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
49 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
H A Dsleep.S127 /* Wait for PLL to lock (assume prediv = 1, 25MHz OSCIN) */
/linux/drivers/clk/davinci/
H A Dpll-da850.c58 "oscin",
177 "oscin",
202 davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip); in da850_pll1_init()
H A Dpll.c31 #define OSCIN_CLK_NAME "oscin"
78 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
80 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
355 * OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN
357 * - OSCIN is the parent clock (on secondary PLL, may come from primary PLL)
387 * We register a clock named "oscin" that serves as the internal in davinci_pll_clk_register()
390 * OBSCLK domains. NB: The various TRMs use "OSCIN" to mean in davinci_pll_clk_register()
/linux/Documentation/devicetree/bindings/media/cec/
H A Damlogic,meson-gx-ao-cec.yaml71 - const: oscin
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt19 wave input on the OSCIN pin instead of using a crystal oscillator.