1 // SPDX-License-Identifier: GPL-2.0
2
3 #include <linux/device.h>
4 #include <linux/err.h>
5 #include <linux/errno.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/property.h>
9
10 #include <drm/drm_mipi_dsi.h>
11 #include <drm/drm_modes.h>
12 #include <drm/drm_of.h>
13 #include <drm/drm_panel.h>
14 #include <drm/drm_probe_helper.h>
15
16 #include <video/mipi_display.h>
17
18 #include "panel-ilitek-ili9806e-core.h"
19
20 struct ili9806e_dsi_panel_desc {
21 const struct drm_display_mode *display_mode;
22 unsigned long mode_flags;
23 enum mipi_dsi_pixel_format format;
24 unsigned int lanes;
25 void (*init_sequence)(struct mipi_dsi_multi_context *ctx);
26 };
27
28 struct ili9806e_dsi_panel {
29 struct mipi_dsi_device *dsi;
30 const struct ili9806e_dsi_panel_desc *desc;
31 enum drm_panel_orientation orientation;
32 };
33
ili9806e_dsi_on(struct ili9806e_dsi_panel * ili9806e)34 static int ili9806e_dsi_on(struct ili9806e_dsi_panel *ili9806e)
35 {
36 struct mipi_dsi_multi_context ctx = { .dsi = ili9806e->dsi };
37
38 if (ili9806e->desc->init_sequence)
39 ili9806e->desc->init_sequence(&ctx);
40
41 mipi_dsi_dcs_exit_sleep_mode_multi(&ctx);
42 mipi_dsi_msleep(&ctx, 120);
43 mipi_dsi_dcs_set_display_on_multi(&ctx);
44
45 return ctx.accum_err;
46 }
47
ili9806e_dsi_off(struct ili9806e_dsi_panel * panel)48 static int ili9806e_dsi_off(struct ili9806e_dsi_panel *panel)
49 {
50 struct mipi_dsi_multi_context ctx = { .dsi = panel->dsi };
51
52 mipi_dsi_dcs_set_display_off_multi(&ctx);
53 mipi_dsi_dcs_enter_sleep_mode_multi(&ctx);
54 mipi_dsi_msleep(&ctx, 120);
55
56 return ctx.accum_err;
57 }
58
ili9806e_dsi_prepare(struct drm_panel * panel)59 static int ili9806e_dsi_prepare(struct drm_panel *panel)
60 {
61 struct ili9806e_dsi_panel *ctx = ili9806e_get_transport(panel);
62 struct device *dev = &ctx->dsi->dev;
63 int ret;
64
65 ret = ili9806e_power_on(dev);
66 if (ret < 0)
67 return ret;
68
69 ret = ili9806e_dsi_on(ctx);
70 if (ret < 0) {
71 ili9806e_power_off(dev);
72 return ret;
73 }
74
75 return 0;
76 }
77
ili9806e_dsi_unprepare(struct drm_panel * panel)78 static int ili9806e_dsi_unprepare(struct drm_panel *panel)
79 {
80 struct ili9806e_dsi_panel *ctx = ili9806e_get_transport(panel);
81 struct device *dev = &ctx->dsi->dev;
82 int ret;
83
84 ili9806e_dsi_off(ctx);
85
86 ret = ili9806e_power_off(dev);
87 if (ret < 0)
88 dev_err(dev, "power off failed: %d\n", ret);
89
90 return ret;
91 }
92
ili9806e_dsi_get_modes(struct drm_panel * panel,struct drm_connector * connector)93 static int ili9806e_dsi_get_modes(struct drm_panel *panel,
94 struct drm_connector *connector)
95 {
96 struct ili9806e_dsi_panel *ctx = ili9806e_get_transport(panel);
97 const struct drm_display_mode *mode = ctx->desc->display_mode;
98
99 return drm_connector_helper_get_modes_fixed(connector, mode);
100 }
101
ili9806e_dsi_get_orientation(struct drm_panel * panel)102 static enum drm_panel_orientation ili9806e_dsi_get_orientation(struct drm_panel *panel)
103 {
104 struct ili9806e_dsi_panel *ctx = ili9806e_get_transport(panel);
105
106 return ctx->orientation;
107 }
108
109 static const struct drm_panel_funcs ili9806e_dsi_funcs = {
110 .prepare = ili9806e_dsi_prepare,
111 .unprepare = ili9806e_dsi_unprepare,
112 .get_modes = ili9806e_dsi_get_modes,
113 .get_orientation = ili9806e_dsi_get_orientation,
114 };
115
ili9806e_dsi_probe(struct mipi_dsi_device * dsi)116 static int ili9806e_dsi_probe(struct mipi_dsi_device *dsi)
117 {
118 struct device *dev = &dsi->dev;
119 struct ili9806e_dsi_panel *ctx;
120 int ret;
121
122 ctx = devm_kzalloc(dev, sizeof(struct ili9806e_dsi_panel), GFP_KERNEL);
123 if (!ctx)
124 return -ENOMEM;
125
126 ctx->desc = device_get_match_data(dev);
127
128 mipi_dsi_set_drvdata(dsi, ctx);
129 ctx->dsi = dsi;
130
131 dsi->mode_flags = ctx->desc->mode_flags;
132 dsi->format = ctx->desc->format;
133 dsi->lanes = ctx->desc->lanes;
134
135 ret = drm_of_get_panel_orientation(dev->of_node, &ctx->orientation);
136 if (ret)
137 return dev_err_probe(dev, ret, "Failed to get orientation\n");
138
139 ret = ili9806e_probe(dev, ctx, &ili9806e_dsi_funcs,
140 DRM_MODE_CONNECTOR_DSI);
141 if (ret)
142 return ret;
143
144 ret = mipi_dsi_attach(dsi);
145 if (ret < 0) {
146 dev_err_probe(dev, ret, "Failed to attach to DSI host\n");
147 ili9806e_remove(dev);
148 return ret;
149 }
150
151 return 0;
152 }
153
ili9806e_dsi_remove(struct mipi_dsi_device * dsi)154 static void ili9806e_dsi_remove(struct mipi_dsi_device *dsi)
155 {
156 mipi_dsi_detach(dsi);
157 ili9806e_remove(&dsi->dev);
158 }
159
com35h3p70ulc_init(struct mipi_dsi_multi_context * ctx)160 static void com35h3p70ulc_init(struct mipi_dsi_multi_context *ctx)
161 {
162 /* Switch to page 1 */
163 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01);
164 /* Interface Settings */
165 mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x18);
166 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01);
167 /* Panel Settings */
168 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x03);
169 mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00);
170 mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x0d);
171 mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x08);
172 mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x08);
173 mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x09);
174 /* Power Control */
175 mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x30);
176 mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x44);
177 mipi_dsi_dcs_write_seq_multi(ctx, 0x42, 0x00);
178 mipi_dsi_dcs_write_seq_multi(ctx, 0x43, 0x89);
179 mipi_dsi_dcs_write_seq_multi(ctx, 0x44, 0x8e);
180 mipi_dsi_dcs_write_seq_multi(ctx, 0x45, 0xd9);
181 mipi_dsi_dcs_write_seq_multi(ctx, 0x46, 0x33);
182 mipi_dsi_dcs_write_seq_multi(ctx, 0x47, 0x33);
183 mipi_dsi_dcs_write_seq_multi(ctx, 0x50, 0x90);
184 mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0x90);
185 mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x00);
186 /* Gamma Settings */
187 mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x00);
188 mipi_dsi_dcs_write_seq_multi(ctx, 0xa1, 0x0c);
189 mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x13);
190 mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x0f);
191 mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x0a);
192 mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x0d);
193 mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x0c);
194 mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x0b);
195 mipi_dsi_dcs_write_seq_multi(ctx, 0xa8, 0x01);
196 mipi_dsi_dcs_write_seq_multi(ctx, 0xa9, 0x06);
197 mipi_dsi_dcs_write_seq_multi(ctx, 0xaa, 0x15);
198 mipi_dsi_dcs_write_seq_multi(ctx, 0xab, 0x07);
199 mipi_dsi_dcs_write_seq_multi(ctx, 0xac, 0x12);
200 mipi_dsi_dcs_write_seq_multi(ctx, 0xad, 0x28);
201 mipi_dsi_dcs_write_seq_multi(ctx, 0xae, 0x20);
202 mipi_dsi_dcs_write_seq_multi(ctx, 0xaf, 0x14);
203 mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00);
204 mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x0c);
205 mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x13);
206 mipi_dsi_dcs_write_seq_multi(ctx, 0xc3, 0x0f);
207 mipi_dsi_dcs_write_seq_multi(ctx, 0xc4, 0x09);
208 mipi_dsi_dcs_write_seq_multi(ctx, 0xc5, 0x0d);
209 mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0x0c);
210 mipi_dsi_dcs_write_seq_multi(ctx, 0xc7, 0x0b);
211 mipi_dsi_dcs_write_seq_multi(ctx, 0xc8, 0x01);
212 mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x06);
213 mipi_dsi_dcs_write_seq_multi(ctx, 0xca, 0x14);
214 mipi_dsi_dcs_write_seq_multi(ctx, 0xcb, 0x07);
215 mipi_dsi_dcs_write_seq_multi(ctx, 0xcc, 0x0f);
216 mipi_dsi_dcs_write_seq_multi(ctx, 0xcd, 0x21);
217 mipi_dsi_dcs_write_seq_multi(ctx, 0xce, 0x17);
218 mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x0a);
219
220 /* Switch to page 7 */
221 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07);
222 /* Power Control */
223 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x00);
224 mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x1d);
225 mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x32);
226
227 /* Switch to page 6 */
228 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06);
229 /* GIP settings */
230 mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x20);
231 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x02);
232 mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x00);
233 mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x02);
234 mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x01);
235 mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x01);
236 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x88);
237 mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x04);
238 mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x03);
239 mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x80);
240 mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x00);
241 mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x00);
242 mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x01);
243 mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x01);
244 mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x00);
245 mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x00);
246 mipi_dsi_dcs_write_seq_multi(ctx, 0x10, 0x55);
247 mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0x50);
248 mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x01);
249 mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x00);
250 mipi_dsi_dcs_write_seq_multi(ctx, 0x14, 0x00);
251 mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0x43);
252 mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x0b);
253 mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x00);
254 mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x00);
255 mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x10);
256 mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x00);
257 mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x00);
258 mipi_dsi_dcs_write_seq_multi(ctx, 0x1c, 0x00);
259 mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x00);
260 mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x01);
261 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x23);
262 mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x45);
263 mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x67);
264 mipi_dsi_dcs_write_seq_multi(ctx, 0x24, 0x01);
265 mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x23);
266 mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x45);
267 mipi_dsi_dcs_write_seq_multi(ctx, 0x27, 0x67);
268 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x02);
269 mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x22);
270 mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x22);
271 mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0x88);
272 mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xaa);
273 mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0xbb);
274 mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0x66);
275 mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0x22);
276 mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x22);
277 mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x22);
278 mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x22);
279 mipi_dsi_dcs_write_seq_multi(ctx, 0x3b, 0x22);
280 mipi_dsi_dcs_write_seq_multi(ctx, 0x3c, 0x22);
281 mipi_dsi_dcs_write_seq_multi(ctx, 0x3d, 0x22);
282 mipi_dsi_dcs_write_seq_multi(ctx, 0x3e, 0x22);
283 mipi_dsi_dcs_write_seq_multi(ctx, 0x3f, 0x22);
284 mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x22);
285 mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x12);
286
287 /* Switch to page 0 */
288 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00);
289 /* Interface Pixel format */
290 mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x60);
291 };
292
293 static const struct drm_display_mode com35h3p70ulc_default_mode = {
294 .clock = 22400,
295 .hdisplay = 480,
296 .hsync_start = 480 + 16,
297 .hsync_end = 480 + 16 + 16,
298 .htotal = 480 + 16 + 16 + 16,
299 .vdisplay = 640,
300 .vsync_start = 640 + 52,
301 .vsync_end = 640 + 52 + 4,
302 .vtotal = 640 + 52 + 4 + 16,
303 .width_mm = 53,
304 .height_mm = 71,
305 };
306
307 static const struct ili9806e_dsi_panel_desc com35h3p70ulc_desc = {
308 .init_sequence = com35h3p70ulc_init,
309 .display_mode = &com35h3p70ulc_default_mode,
310 .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
311 MIPI_DSI_MODE_LPM,
312 .format = MIPI_DSI_FMT_RGB888,
313 .lanes = 2,
314 };
315
dmt028vghmcmi_1d_init(struct mipi_dsi_multi_context * ctx)316 static void dmt028vghmcmi_1d_init(struct mipi_dsi_multi_context *ctx)
317 {
318 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01);
319 mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x10);
320 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01);
321 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x03);
322 mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00);
323 mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x06);
324 mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x00);
325 mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x07);
326 mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x00);
327 mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x16);
328 mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x44);
329 mipi_dsi_dcs_write_seq_multi(ctx, 0x42, 0x00);
330 mipi_dsi_dcs_write_seq_multi(ctx, 0x43, 0x83);
331 mipi_dsi_dcs_write_seq_multi(ctx, 0x44, 0x89);
332 mipi_dsi_dcs_write_seq_multi(ctx, 0x45, 0x8a);
333 mipi_dsi_dcs_write_seq_multi(ctx, 0x46, 0x44);
334 mipi_dsi_dcs_write_seq_multi(ctx, 0x47, 0x44);
335 mipi_dsi_dcs_write_seq_multi(ctx, 0x50, 0x78);
336 mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0x78);
337 mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x00);
338 mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x6c);
339 mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x00);
340 mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x6c);
341 mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x00);
342 /* Gamma settings */
343 mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x00);
344 mipi_dsi_dcs_write_seq_multi(ctx, 0xa1, 0x09);
345 mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x14);
346 mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x09);
347 mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x05);
348 mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x0a);
349 mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x07);
350 mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x07);
351 mipi_dsi_dcs_write_seq_multi(ctx, 0xa8, 0x08);
352 mipi_dsi_dcs_write_seq_multi(ctx, 0xa9, 0x0b);
353 mipi_dsi_dcs_write_seq_multi(ctx, 0xaa, 0x0c);
354 mipi_dsi_dcs_write_seq_multi(ctx, 0xab, 0x05);
355 mipi_dsi_dcs_write_seq_multi(ctx, 0xac, 0x0a);
356 mipi_dsi_dcs_write_seq_multi(ctx, 0xad, 0x19);
357 mipi_dsi_dcs_write_seq_multi(ctx, 0xae, 0x0b);
358 mipi_dsi_dcs_write_seq_multi(ctx, 0xaf, 0x00);
359
360 mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00);
361 mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x0c);
362 mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x14);
363 mipi_dsi_dcs_write_seq_multi(ctx, 0xc3, 0x11);
364 mipi_dsi_dcs_write_seq_multi(ctx, 0xc4, 0x05);
365 mipi_dsi_dcs_write_seq_multi(ctx, 0xc5, 0x0c);
366 mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0x08);
367 mipi_dsi_dcs_write_seq_multi(ctx, 0xc7, 0x03);
368 mipi_dsi_dcs_write_seq_multi(ctx, 0xc8, 0x06);
369 mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x0a);
370 mipi_dsi_dcs_write_seq_multi(ctx, 0xca, 0x10);
371 mipi_dsi_dcs_write_seq_multi(ctx, 0xcb, 0x05);
372 mipi_dsi_dcs_write_seq_multi(ctx, 0xcc, 0x0d);
373 mipi_dsi_dcs_write_seq_multi(ctx, 0xcd, 0x15);
374 mipi_dsi_dcs_write_seq_multi(ctx, 0xce, 0x13);
375 mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x00);
376
377 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07);
378 mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x22);
379 mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x1d);
380 mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x77);
381 mipi_dsi_dcs_write_seq_multi(ctx, 0xe1, 0x79);
382 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x13);
383
384 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06);
385 /* GIP 0 */
386 mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x21);
387 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0a);
388 mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x00);
389 mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x05);
390 mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x01);
391 mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x01);
392 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x98);
393 mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x06);
394 mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x01);
395 mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x00);
396 mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x00);
397 mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x00);
398 mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x01);
399 mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x01);
400 mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x00);
401 mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x00);
402 mipi_dsi_dcs_write_seq_multi(ctx, 0x10, 0xf7);
403 mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0xf0);
404 mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x00);
405 mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x00);
406 mipi_dsi_dcs_write_seq_multi(ctx, 0x14, 0x00);
407 mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0xc0);
408 mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x08);
409 mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x00);
410 mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x00);
411 mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x00);
412 mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x00);
413 mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x00);
414 mipi_dsi_dcs_write_seq_multi(ctx, 0x1c, 0x00);
415 mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x00);
416 /* GIP 1 */
417 mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x01);
418 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x23);
419 mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x44);
420 mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x67);
421 mipi_dsi_dcs_write_seq_multi(ctx, 0x24, 0x01);
422 mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x23);
423 mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x45);
424 mipi_dsi_dcs_write_seq_multi(ctx, 0x27, 0x67);
425 /* GIP 2 */
426 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x01);
427 mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x22);
428 mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x22);
429 mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0xbc);
430 mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xad);
431 mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0xda);
432 mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0xcb);
433 mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0x22);
434 mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x55);
435 mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x76);
436 mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x67);
437 mipi_dsi_dcs_write_seq_multi(ctx, 0x3b, 0x88);
438 mipi_dsi_dcs_write_seq_multi(ctx, 0x3c, 0x22);
439 mipi_dsi_dcs_write_seq_multi(ctx, 0x3d, 0x11);
440 mipi_dsi_dcs_write_seq_multi(ctx, 0x3e, 0x00);
441 mipi_dsi_dcs_write_seq_multi(ctx, 0x3f, 0x22);
442 mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x22);
443
444 mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x10);
445 mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x10);
446 mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x13);
447
448 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00);
449 };
450
451 static const struct drm_display_mode dmt028vghmcmi_1d_default_mode = {
452 .clock = 22000,
453
454 .hdisplay = 480,
455 .hsync_start = 480 + 20,
456 .hsync_end = 480 + 20 + 4,
457 .htotal = 480 + 20 + 4 + 10,
458
459 .vdisplay = 640,
460 .vsync_start = 640 + 40,
461 .vsync_end = 640 + 40 + 4,
462 .vtotal = 640 + 40 + 4 + 20,
463
464 .width_mm = 53,
465 .height_mm = 79,
466
467 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
468 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
469 };
470
471 static const struct ili9806e_dsi_panel_desc dmt028vghmcmi_1d_desc = {
472 .init_sequence = dmt028vghmcmi_1d_init,
473 .display_mode = &dmt028vghmcmi_1d_default_mode,
474 .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
475 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
476 .format = MIPI_DSI_FMT_RGB888,
477 .lanes = 2,
478 };
479
480 static const struct of_device_id ili9806e_dsi_of_match[] = {
481 { .compatible = "densitron,dmt028vghmcmi-1d", .data = &dmt028vghmcmi_1d_desc },
482 { .compatible = "ortustech,com35h3p70ulc", .data = &com35h3p70ulc_desc },
483 { }
484 };
485 MODULE_DEVICE_TABLE(of, ili9806e_dsi_of_match);
486
487 static struct mipi_dsi_driver ili9806e_dsi_driver = {
488 .driver = {
489 .name = "ili9806e-dsi",
490 .of_match_table = ili9806e_dsi_of_match,
491 },
492 .probe = ili9806e_dsi_probe,
493 .remove = ili9806e_dsi_remove,
494 };
495 module_mipi_dsi_driver(ili9806e_dsi_driver);
496
497 MODULE_AUTHOR("Gunnar Dibbern <gunnar.dibbern@lht.dlh.de>");
498 MODULE_AUTHOR("Michael Walle <mwalle@kernel.org>");
499 MODULE_DESCRIPTION("Ilitek ILI9806E Controller DSI Driver");
500 MODULE_LICENSE("GPL");
501