/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra124-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 emc_icc_dvfs_opp_table: opp-table-emc { 5 compatible = "operating-points-v2"; 7 opp-12750000-800 { 8 opp-microvolt = <800000 800000 1150000>; 9 opp-hz = /bits/ 64 <12750000>; 10 opp-supported-hw = <0x0003>; 13 opp-12750000-950 { 14 opp-microvolt = <950000 950000 1150000>; 15 opp-hz = /bits/ 64 <12750000>; [all …]
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H A D | tegra20-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 core_opp_table: opp-table-core { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 core_opp_950: opp-950000 { 9 opp-microvolt = <950000 950000 1300000>; 10 opp-level = <950000>; 13 core_opp_1000: opp-1000000 { 14 opp-microvolt = <1000000 1000000 1300000>; 15 opp-level = <1000000>; [all …]
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/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra132-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 /* EMC DVFS OPP table */ 5 emc_icc_dvfs_opp_table: opp-table-dvfs0 { 6 compatible = "operating-points-v2"; 8 opp-12750000-800 { 9 opp-microvolt = <800000 800000 1150000>; 10 opp-hz = /bits/ 64 <12750000>; 11 opp-supported-hw = <0x0003>; 14 opp-12750000-950 { 15 opp-microvolt = <950000 950000 1150000>; [all …]
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/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos5800.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 20 compatible = "samsung,exynos5800-clock", "syscon"; 24 opp-2000000000 { 25 opp-hz = /bits/ 64 <2000000000>; 26 opp-microvolt = <1312500 1312500 1500000>; 27 clock-latency-ns = <140000>; 29 opp-1900000000 { 30 opp-hz = /bits/ 64 <1900000000>; 31 opp-microvolt = <1262500 1262500 1500000>; 32 clock-latency-ns = <140000>; [all …]
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H A D | exynos4212.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 23 #address-cells = <1>; 24 #size-cells = <0>; 26 cpu-map { 39 compatible = "arm,cortex-a9"; 42 clock-names = "cpu"; 43 operating-points-v2 = <&cpu0_opp_table>; 44 #cooling-cells = <2>; /* min followed by max */ 49 compatible = "arm,cortex-a9"; 52 clock-names = "cpu"; [all …]
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H A D | exynos4412.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 23 #address-cells = <1>; 24 #size-cells = <0>; 26 cpu-map { 45 compatible = "arm,cortex-a9"; 48 clock-names = "cpu"; 49 operating-points-v2 = <&cpu0_opp_table>; 50 #cooling-cells = <2>; /* min followed by max */ 55 compatible = "arm,cortex-a9"; 58 clock-names = "cpu"; [all …]
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/linux/Documentation/devicetree/bindings/opp/ |
H A D | operating-points-v2-ti-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/operating-points-v2-ti-cpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI CPU OPP (Operating Performance Points) 12 OPP vary based on the silicon variant used. The data sheet sections 18 This document extends the operating-points-v2 binding by providing 22 - Dhruva Gole <d-gole@ti.com> 25 - $ref: opp-v2-base.yaml# 29 const: operating-points-v2-ti-cpu [all …]
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/linux/Documentation/devicetree/bindings/display/msm/ |
H A D | qcom,sm8150-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 17 $ref: /schemas/display/msm/mdss-common.yaml# 22 - const: qcom,sm8150-mdss 26 - description: Display AHB clock from gcc 27 - description: Display hf axi clock [all …]
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H A D | qcom,sm8250-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 17 $ref: /schemas/display/msm/mdss-common.yaml# 21 const: qcom,sm8250-mdss 25 - description: Display AHB clock from gcc 26 - description: Display hf axi clock [all …]
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H A D | qcom,sm7150-dpu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-dpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Danila Tikhonov <danila@jiaxyga.com> 12 $ref: /schemas/display/msm/dpu-common.yaml# 16 const: qcom,sm7150-dpu 20 - description: Address offset and size for mdp register set 21 - description: Address offset and size for vbif register set 23 reg-names: [all …]
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H A D | qcom,sm8350-dpu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Robert Foss <robert.foss@linaro.org> 12 $ref: /schemas/display/msm/dpu-common.yaml# 16 const: qcom,sm8350-dpu 20 - description: Address offset and size for mdp register set 21 - description: Address offset and size for vbif register set 23 reg-names: [all …]
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H A D | qcom,sm8350-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Robert Foss <robert.foss@linaro.org> 13 MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like 16 $ref: /schemas/display/msm/mdss-common.yaml# 21 - const: qcom,sm8350-mdss 25 - description: Display AHB clock from gcc 26 - description: Display hf axi clock [all …]
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H A D | qcom,sm8650-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Neil Armstrong <neil.armstrong@linaro.org> 13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like 16 $ref: /schemas/display/msm/mdss-common.yaml# 20 const: qcom,sm8650-mdss 24 - description: Display AHB 25 - description: Display hf AXI [all …]
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H A D | qcom,sm8550-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Neil Armstrong <neil.armstrong@linaro.org> 13 SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like 16 $ref: /schemas/display/msm/mdss-common.yaml# 20 const: qcom,sm8550-mdss 24 - description: Display MDSS AHB 25 - description: Display AHB [all …]
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H A D | qcom,sc7180-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 17 $ref: /schemas/display/msm/mdss-common.yaml# 21 const: qcom,sc7180-mdss 25 - description: Display AHB clock from gcc 26 - description: Display AHB clock from dispcc [all …]
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H A D | qcom,sm8450-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 13 SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like 16 $ref: /schemas/display/msm/mdss-common.yaml# 20 const: qcom,sm8450-mdss 24 - description: Display AHB 25 - description: Display hf AXI [all …]
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H A D | qcom,sm7150-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Danila Tikhonov <danila@jiaxyga.com> 13 SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like 16 $ref: /schemas/display/msm/mdss-common.yaml# 20 const: qcom,sm7150-mdss 24 - description: Display ahb clock from gcc 25 - description: Display hf axi clock [all …]
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H A D | qcom,sc7280-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 17 $ref: /schemas/display/msm/mdss-common.yaml# 21 const: qcom,sc7280-mdss 25 - description: Display AHB clock from gcc 26 - description: Display AHB clock from dispcc [all …]
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/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3588j.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "rk3588-extra.dtsi" 10 cluster0_opp_table: opp-table-cluster0 { 11 compatible = "operating-points-v2"; 12 opp-shared; 14 opp-1416000000 { 15 opp-hz = /bits/ 64 <1416000000>; 16 opp-microvolt = <750000 750000 950000>; 17 clock-latency-ns = <40000>; 18 opp-suspend; [all …]
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H A D | rk3588-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 cluster0_opp_table: opp-table-cluster0 { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 opp-1008000000 { 9 opp-hz = /bits/ 64 <1008000000>; 10 opp-microvolt = <675000 675000 950000>; 11 clock-latency-ns = <40000>; 13 opp-1200000000 { 14 opp-hz = /bits/ 64 <1200000000>; [all …]
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/linux/Documentation/devicetree/bindings/gpu/ |
H A D | arm,mali-valhall-csf.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liviu Dudau <liviu.dudau@arm.com> 11 - Boris Brezillon <boris.brezillon@collabora.com> 15 pattern: '^gpu@[a-f0-9]+$' 19 - items: 20 - enum: 21 - rockchip,rk3588-mali [all …]
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | sa8540p.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 9 /delete-node/ &cpu0_opp_table; 10 /delete-node/ &cpu4_opp_table; 13 cpu0_opp_table: opp-table-cpu0 { 14 compatible = "operating-points-v2"; 15 opp-shared; 17 opp-300000000 { 18 opp-hz = /bits/ 64 <300000000>; 19 opp-peak-kBps = <(300000 * 32)>; 21 opp-403200000 { [all …]
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap36xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/media/omap3-isp.h> 21 operating-points-v2 = <&cpu0_opp_table>; 23 vbb-supply = <&abb_mpu_iva>; 24 clock-latency = <300000>; /* From omap-cpufreq driver */ 25 #cooling-cells = <2>; 29 cpu0_opp_table: opp-table { 30 compatible = "operating-points-v2-ti-cpu"; [all …]
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H A D | am3517.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 11 /delete-node/ &aes1_target; 12 /delete-node/ &aes2_target; 24 operating-points-v2 = <&cpu0_opp_table>; 26 clock-latency = <300000>; /* From legacy driver */ 30 cpu0_opp_table: opp-table { 31 compatible = "operating-points-v2-ti-cpu"; 38 opp-50-300000000 { 40 opp-hz = /bits/ 64 <300000000>; [all …]
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H A D | am33xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/pinctrl/am33xx.h> 11 #include <dt-bindings/clock/am3.h> 15 interrupt-parent = <&intc>; 16 #address-cells = <1>; 17 #size-cells = <1>; 30 d-can0 = &dcan0; [all …]
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