Searched +full:opp +full:- +full:1100000000 (Results 1 – 15 of 15) sorted by relevance
/freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
H A D | tegra30-cpu-opp-microvolt.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 cpu0_opp_table: opp-table-cpu0 { 5 opp-51000000-800 { 6 opp-microvolt = <800000 800000 1250000>; 9 opp-51000000-850 { 10 opp-microvolt = <850000 850000 1250000>; 13 opp-51000000-912 { 14 opp-microvolt = <912000 912000 1250000>; 17 opp-102000000-800 { 18 opp-microvolt = <800000 800000 1250000>; [all …]
|
H A D | tegra30-cpu-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 cpu0_opp_table: opp-table-cpu0 { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 opp-51000000-800 { 9 clock-latency-ns = <100000>; 10 opp-supported-hw = <0x1F 0x31FE>; 11 opp-hz = /bits/ 64 <51000000>; 14 opp-51000000-850 { 15 clock-latency-ns = <100000>; [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/opp/ |
H A D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic OPP (Operating Performance Points) 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 - $ref: opp-v2-base.yaml# 17 const: operating-points-v2 22 - | 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states [all …]
|
H A D | opp.txt | 1 Generic OPP (Operating Performance Points) Bindings 2 ---------------------------------------------------- 4 Devices work at voltage-current-frequency combinations and some implementations 10 This document contain multiple versions of OPP binding and only one of them 13 Binding 1: operating-points 16 This binding only supports voltage-frequency pairs. 19 - operating-points: An array of 2-tuples items, and each item consists 20 of frequency and voltage like <freq-kHz vol-uV>. 27 compatible = "arm,cortex-a9"; 29 next-level-cache = <&L2>; [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/power/ |
H A D | power_domain.txt | 12 #power-domain-cells property in the PM domain provider node. 16 See power-domain.yaml. 21 - power-domains : A list of PM domain specifiers, as defined by bindings of 25 - power-domain-names : A list of power domain name strings sorted in the same 26 order as the power-domains property. Consumers drivers will use 27 power-domain-names to match power domains with power-domains 32 leaky-device@12350000 { 33 compatible = "foo,i-leak-current"; 35 power-domains = <&power 0>; 36 power-domain-names = "io"; [all …]
|
/freebsd/sys/contrib/device-tree/src/arm/samsung/ |
H A D | exynos5800.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 20 compatible = "samsung,exynos5800-clock", "syscon"; 24 opp-2000000000 { 25 opp-hz = /bits/ 64 <2000000000>; 26 opp-microvolt = <1312500 1312500 1500000>; 27 clock-latency-ns = <140000>; 29 opp-1900000000 { 30 opp-hz = /bits/ 64 <1900000000>; 31 opp-microvolt = <1262500 1262500 1500000>; 32 clock-latency-ns = <140000>; [all …]
|
H A D | exynos4212.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 23 #address-cells = <1>; 24 #size-cells = <0>; 26 cpu-map { 39 compatible = "arm,cortex-a9"; 42 clock-names = "cpu"; 43 operating-points-v2 = <&cpu0_opp_table>; 44 #cooling-cells = <2>; /* min followed by max */ 49 compatible = "arm,cortex-a9"; 52 clock-names = "cpu"; [all …]
|
H A D | exynos4412.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 23 #address-cells = <1>; 24 #size-cells = <0>; 26 cpu-map { 45 compatible = "arm,cortex-a9"; 48 clock-names = "cpu"; 49 operating-points-v2 = <&cpu0_opp_table>; 50 #cooling-cells = <2>; /* min followed by max */ 55 compatible = "arm,cortex-a9"; 58 clock-names = "cpu"; [all …]
|
H A D | exynos5420.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 14 #include <dt-bindings/clock/exynos5420.h> 15 #include <dt-bindings/clock/exynos-audss-clk.h> 16 #include <dt-bindings/interrupt-controller/arm-gic.h> 37 bus_disp1: bus-disp1 { 38 compatible = "samsung,exynos-bus"; 40 clock-names = "bus"; 44 bus_disp1_fimd: bus-disp1-fimd { 45 compatible = "samsung,exynos-bus"; 47 clock-names = "bus"; [all …]
|
H A D | exynos5250.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 17 #include <dt-bindings/clock/exynos5250.h> 19 #include "exynos4-cpu-thermal.dtsi" 20 #include <dt-bindings/clock/exynos-audss-clk.h> 46 #address-cells = <1>; 47 #size-cells = <0>; 49 cpu-map { 62 compatible = "arm,cortex-a15"; 65 clock-names = "cpu"; 66 operating-points-v2 = <&cpu0_opp_table>; [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/socionext/ |
H A D | uniphier-ld20.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gi [all...] |
/freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
H A D | ipq5332.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 8 #include <dt-bindings/clock/qcom,apss-ipq.h> 9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h> 10 #include <dt-bindings/interconnect/qcom,ipq5332.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 19 sleep_clk: sleep-clk { [all …]
|
H A D | msm8976.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno 9 #include <dt-bindings/clock/qcom,gcc-msm8976.h> 10 #include <dt-bindings/clock/qcom,rpmcc.h> 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/interrupt-controller/irq.h> 14 #include <dt-bindings/power/qcom-rpmpd.h> 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; [all …]
|
H A D | x1e80100.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/clock/qcom,rpmh.h> 7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h> 10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 12 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/interconnect/qcom,icc.h> 14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/exynos/ |
H A D | exynos5433.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 16 #include <dt-bindings/clock/exynos5433.h> 17 #include <dt-bindings/interrupt-controller/arm-gic.h> 21 #address-cells = <2>; 22 #size-cells = <2>; 24 interrupt-parent = <&gic>; 26 arm-a53-pmu { 27 compatible = "arm,cortex-a53-pmu"; 32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 35 arm-a57-pmu { [all …]
|