| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | spec_operation.json | 12 "PublicDescription": "Counts operations that have been speculatively executed."
16 …ublicDescription": "Counts micro-operations speculatively executed. This is the count of the numbe…
20 …operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instr…
24 …"PublicDescription": "Counts unaligned memory write operations issued by the CPU. This event count…
28 …"PublicDescription": "Counts unaligned memory operations issued by the CPU. This event counts unal…
32 …"PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: …
36 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and …
40 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and …
44 … "PublicDescription": "Counts store-exclusive operations that have been speculatively executed."
48 …: "Counts speculatively executed load operations including Single Instruction Multiple Data (SIMD)…
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| H A D | tlb.json | 12 …tions can be broken up into multiple memory operations. This event does not count TLB maintenance …
20 …refills caused by memory operations from both data and instruction fetch, except for those caused …
24 …ublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations."
28 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
32 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
36 …"PublicDescription": "Counts level 1 data TLB refills caused by memory read operations. If there a…
40 …on": "Counts level 1 data TLB refills caused by data side memory write operations. If there are mu…
44 …memory read operations. This event counts whether the access hits or misses in the TLB. This event…
48 …emory write operations. This event counts whether the access hits or misses in the TLB. This event…
52 …lls caused by memory read operations from both data and instruction fetch except for those caused …
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| H A D | l1d_cache.json | 4 …el 1 data cache refills caused by speculatively executed load or store operations that missed in t…
8 …ache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (n…
12 …and cache write-backs from snoops or cache maintenance operations. The following cache operations …
16 …ts cache line refills into the level 1 data cache from any memory read operations, that incurred a…
20 …ounts level 1 data cache accesses from any load operation. Atomic load operations that resolve in …
24 …re operations. This event also counts accesses caused by a DC ZVA (data cache zero, specified by v…
44 …cache line allocation. This event does not count evictions caused by cache maintenance operations."
48 …t of a coherency operation made by another CPU. Event count includes cache maintenance operations."
52 …sed by:\n\n- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast ca…
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| H A D | metrics.json | 33 …"BriefDescription": "This metric measures branch operations as a percentage of operations speculat…
35 "ScaleUnit": "1percent of operations"
40 …"BriefDescription": "This metric measures crypto operations as a percentage of operations speculat…
42 "ScaleUnit": "1percent of operations"
72 …BriefDescription": "This metric measures scalar integer operations as a percentage of operations s…
74 "ScaleUnit": "1percent of operations"
205 …"BriefDescription": "This metric measures load operations as a percentage of operations speculativ…
207 "ScaleUnit": "1percent of operations"
215 …scription": "This metric measures scalar floating point operations as a percentage of operations s…
217 "ScaleUnit": "1percent of operations"
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | spec_operation.json | 12 "PublicDescription": "Counts operations that have been speculatively executed."
16 "PublicDescription": "Counts micro-operations speculatively executed. This is the count of the number of micro-operations dispatched in a cycle."
20 "PublicDescription": "Counts unaligned memory read operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instruction), even if they are subsequently issued as multiple aligned accesses. The event does not count preload operations (PLD, PLI)."
24 "PublicDescription": "Counts unaligned memory write operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instruction), even if they are subsequently issued as multiple aligned accesses."
28 "PublicDescription": "Counts unaligned memory operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instruction), even if they are subsequently issued as multiple aligned accesses."
32 "PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. For example: LDREX, LDX"
36 "PublicDescription": "Counts store-exclusive operations that have been speculatively executed and have successfully completed the store operation."
40 "PublicDescription": "Counts store-exclusive operations tha
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| H A D | tlb.json | 12 "PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operation. Note that load or store instructions can be broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 "PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, except for those caused by TLB maintenance operations and hardware prefetches."
24 "PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations."
28 "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
32 "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations."
36 "PublicDescription": "Counts level 1 data TLB refills caused by memory read operations. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an Address Translation (AT) instruction."
40 "PublicDescription": "Counts level 1 data TLB refills caused by data side memory write operations. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count with an access from an Address Translation (AT) instruction."
44 "PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations
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| H A D | sve.json | 4 "PublicDescription": "Counts speculatively executed operations that are SVE operations."
8 "PublicDescription": "Counts speculatively executed predicated SVE operations."
12 …"PublicDescription": "Counts speculatively executed predicated SVE operations with no active predi…
16 …"PublicDescription": "Counts speculatively executed predicated SVE operations with all predicate e…
20 …"PublicDescription": "Counts speculatively executed predicated SVE operations with at least one bu…
24 …"PublicDescription": "Counts speculatively executed predicated SVE operations with at least one no…
28 … "PublicDescription": "Counts speculatively executed SVE first fault or non-fault load operations."
32 …ion": "Counts speculatively executed SVE first fault or non-fault load operations that clear at le…
36 …"PublicDescription": "Counts speculatively executed Advanced SIMD or SVE integer operations with t…
40 …"PublicDescription": "Counts speculatively executed Advanced SIMD or SVE integer operations with t…
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| H A D | l1d_cache.json | 4 "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line."
8 "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) counts as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted."
12 "PublicDescription": "Counts write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache and allocated in the L2 cache or dirty data is written to the L2 and possibly to the next level of cache. This event counts both victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidations which do not result in data being transferred out of the L1 (such as evictions of clean data),\n2. Full line writes which write to L2 without writing L1, such as write streaming mode."
16 "PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read operations, that incurred additional latency."
20 "PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a write access and read access."
24 "PublicDescription": "Counts level 1 data cache accesses generated by store operations. This event also counts accesses caused by a DC ZVA (data cache zero, specified by virtual address) instruction. Near atomic operations tha
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | spec_operation.json | 12 "PublicDescription": "Counts operations that have been speculatively executed."
16 …operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instr…
20 …"PublicDescription": "Counts unaligned memory write operations issued by the CPU. This event count…
24 …"PublicDescription": "Counts unaligned memory operations issued by the CPU. This event counts unal…
28 …"PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: …
32 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and …
36 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and …
40 … "PublicDescription": "Counts store-exclusive operations that have been speculatively executed."
44 …: "Counts speculatively executed load operations including Single Instruction Multiple Data (SIMD)…
48 … "Counts speculatively executed store operations including Single Instruction Multiple Data (SIMD)…
[all …]
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| H A D | tlb.json | 12 …tions can be broken up into multiple memory operations. This event does not count TLB maintenance …
20 …refills caused by memory operations from both data and instruction fetch, except for those caused …
24 …ublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations."
28 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
32 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
36 …"PublicDescription": "Counts level 1 data TLB refills caused by memory read operations. If there a…
40 …on": "Counts level 1 data TLB refills caused by data side memory write operations. If there are mu…
44 …memory read operations. This event counts whether the access hits or misses in the TLB. This event…
48 …emory write operations. This event counts whether the access hits or misses in the TLB. This event…
52 …lls caused by memory read operations from both data and instruction fetch except for those caused …
[all …]
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| H A D | metrics.json | 26 …"BriefDescription": "This metric measures branch operations as a percentage of operations speculat…
28 "ScaleUnit": "1percent of operations"
33 …"BriefDescription": "This metric measures crypto operations as a percentage of operations speculat…
35 "ScaleUnit": "1percent of operations"
61 …BriefDescription": "This metric measures scalar integer operations as a percentage of operations s…
63 "ScaleUnit": "1percent of operations"
194 …"BriefDescription": "This metric measures load operations as a percentage of operations speculativ…
196 "ScaleUnit": "1percent of operations"
201 …scription": "This metric measures scalar floating point operations as a percentage of operations s…
203 "ScaleUnit": "1percent of operations"
[all …]
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| H A D | l1d_cache.json | 4 …el 1 data cache refills caused by speculatively executed load or store operations that missed in t…
8 …ache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (n…
12 …and cache write-backs from snoops or cache maintenance operations. The following cache operations …
16 …ounts level 1 data cache accesses from any load operation. Atomic load operations that resolve in …
20 …re operations. This event also counts accesses caused by a DC ZVA (data cache zero, specified by v…
40 …cache line allocation. This event does not count evictions caused by cache maintenance operations."
44 …t of a coherency operation made by another CPU. Event count includes cache maintenance operations."
48 …sed by:\n\n- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast ca…
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| /linux/tools/perf/pmu-events/arch/arm64/ |
| H A D | common-and-microarch.json | 321 "PublicDescription": "Micro-operation speculatively executed. The counter counts the number of operations executed by the processing element, including those that are executed speculatively and would not be executed in a simple sequential execution of the program.",
525 "PublicDescription": "ASE operations speculatively executed",
528 "BriefDescription": "ASE operations speculatively executed"
531 "PublicDescription": "SVE operations speculatively executed",
534 "BriefDescription": "SVE operations speculatively executed"
542 "PublicDescription": "Microarchitectural operation, Operations speculatively executed.",
545 "BriefDescription": "Microarchitectural operation, Operations speculatively executed."
548 "PublicDescription": "SVE Math accelerator Operations speculatively executed.",
551 "BriefDescription": "SVE Math accelerator Operations speculatively executed."
554 "PublicDescription": "Floating-point Operations speculativel
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| /linux/tools/memory-model/Documentation/ |
| H A D | ordering.txt | 2 operations provided by the Linux-kernel memory model (LKMM).
9 operations in decreasing order of strength:
12 all of the CPU's prior operations against some or all of its
13 subsequent operations.
15 2. Ordered memory accesses. These operations order themselves
23 some of these "unordered" operations provide limited ordering
62 o Value-returning RMW atomic operations whose names do not end in
82 Second, some RMW atomic operations provide full ordering. These
83 operations include value-returning RMW atomic operations (that is, those
86 cmpxchg(), and xchg(). Note that conditional RMW atomic operations such
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| /linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/ |
| H A D | instruction.json | 66 …"PublicDescription": "This event counts architecturally executed zero blocking operations due to t…
69 …"BriefDescription": "This event counts architecturally executed zero blocking operations due to th…
72 … "PublicDescription": "This event counts architecturally executed floating-point move operations.",
75 "BriefDescription": "This event counts architecturally executed floating-point move operations."
78 …"PublicDescription": "This event counts architecturally executed operations that using predicate r…
81 …"BriefDescription": "This event counts architecturally executed operations that using predicate re…
84 …cDescription": "This event counts architecturally executed inter-element manipulation operations.",
87 …efDescription": "This event counts architecturally executed inter-element manipulation operations."
90 …Description": "This event counts architecturally executed inter-register manipulation operations.",
93 …fDescription": "This event counts architecturally executed inter-register manipulation operations."
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| /linux/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/ |
| H A D | uncore-hha.json | 5 "BriefDescription": "The number of all operations received by the HHA",
6 "PublicDescription": "The number of all operations received by the HHA",
12 "BriefDescription": "The number of all operations received by the HHA from another socket",
13 "PublicDescription": "The number of all operations received by the HHA from another socket",
19 …"BriefDescription": "The number of all operations received by the HHA from another SCCL in this so…
20 …"PublicDescription": "The number of all operations received by the HHA from another SCCL in this s…
26 "BriefDescription": "Count of the number of operations that HHA has received from CCIX",
27 "PublicDescription": "Count of the number of operations that HHA has received from CCIX",
48 "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
49 "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",
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| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| H A D | metrics.json | 75 …iefDescription": "This metric measures advanced SIMD operations as a percentage of total operation…
77 "ScaleUnit": "100percent of operations"
82 …"BriefDescription": "This metric measures crypto operations as a percentage of operations speculat…
84 "ScaleUnit": "100percent of operations"
89 "BriefDescription": "Giga-floating point operations per second",
95 …BriefDescription": "This metric measures scalar integer operations as a percentage of operations s…
97 "ScaleUnit": "100percent of operations"
109 …"BriefDescription": "This metric measures load operations as a percentage of operations speculativ…
111 "ScaleUnit": "100percent of operations"
118 "ScaleUnit": "100percent of operations"
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | floating-point.json | 6 …operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This eve…
13 …operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This eve…
20 …operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This eve…
27 …operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This eve…
34 …operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This eve…
41 …operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This eve…
48 …operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how bus…
55 …operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how bus…
62 …operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how bus…
69 …operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how bus…
|
| /linux/Documentation/ |
| H A D | atomic_bitops.txt | 5 While our bitmap_{}() functions are non-atomic, we have a number of operations
12 The single bit operations are:
18 RMW atomic operations without return value:
23 RMW atomic operations with return value:
33 All RMW atomic operations have a '__' prefixed variant which is non-atomic.
47 The test_and_{}_bit() operations return the original value of the bit.
55 - non-RMW operations are unordered;
57 - RMW operations that have no return value are unordered;
59 - RMW operations that have a return value are fully ordered.
61 - RMW operations that are conditional are fully ordered.
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| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/ |
| H A D | metrics.json | 75 …iefDescription": "This metric measures advanced SIMD operations as a percentage of total operation…
77 "ScaleUnit": "1percent of operations"
82 …"BriefDescription": "This metric measures crypto operations as a percentage of operations speculat…
84 "ScaleUnit": "1percent of operations"
89 "BriefDescription": "Giga-floating point operations per second",
95 …BriefDescription": "This metric measures scalar integer operations as a percentage of operations s…
97 "ScaleUnit": "1percent of operations"
109 …"BriefDescription": "This metric measures load operations as a percentage of operations speculativ…
111 "ScaleUnit": "1percent of operations"
118 "ScaleUnit": "1percent of operations"
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| /linux/Documentation/core-api/ |
| H A D | this_cpu_ops.rst | 2 this_cpu operations
8 this_cpu operations are a way of optimizing access to per cpu
14 this_cpu operations add a per cpu variable offset to the processor
24 Read-modify-write operations are of particular interest. Frequently
39 (remote write operations) of local RMW operations via this_cpu_*.
41 The main use of the this_cpu operations has been to optimize counter
42 operations.
44 The following this_cpu() operations with implied preemption protection
45 are defined. These operations can be used without worrying about
64 Inner working of this_cpu operations
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| /linux/tools/perf/pmu-events/arch/x86/westmereex/ |
| H A D | floating-point.json | 86 "BriefDescription": "Computational floating-point operations executed",
118 "BriefDescription": "128 bit SIMD integer pack operations",
126 "BriefDescription": "128 bit SIMD integer arithmetic operations",
134 "BriefDescription": "128 bit SIMD integer logical operations",
142 "BriefDescription": "128 bit SIMD integer multiply operations",
150 "BriefDescription": "128 bit SIMD integer shift operations",
158 "BriefDescription": "128 bit SIMD integer shuffle/move operations",
166 "BriefDescription": "128 bit SIMD integer unpack operations",
174 "BriefDescription": "SIMD integer 64 bit pack operations",
182 "BriefDescription": "SIMD integer 64 bit arithmetic operations",
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| /linux/tools/perf/pmu-events/arch/x86/westmereep-dp/ |
| H A D | floating-point.json | 86 "BriefDescription": "Computational floating-point operations executed",
118 "BriefDescription": "128 bit SIMD integer pack operations",
126 "BriefDescription": "128 bit SIMD integer arithmetic operations",
134 "BriefDescription": "128 bit SIMD integer logical operations",
142 "BriefDescription": "128 bit SIMD integer multiply operations",
150 "BriefDescription": "128 bit SIMD integer shift operations",
158 "BriefDescription": "128 bit SIMD integer shuffle/move operations",
166 "BriefDescription": "128 bit SIMD integer unpack operations",
174 "BriefDescription": "SIMD integer 64 bit pack operations",
182 "BriefDescription": "SIMD integer 64 bit arithmetic operations",
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| /linux/tools/perf/pmu-events/arch/x86/nehalemep/ |
| H A D | floating-point.json | 86 "BriefDescription": "Computational floating-point operations executed",
118 "BriefDescription": "128 bit SIMD integer pack operations",
126 "BriefDescription": "128 bit SIMD integer arithmetic operations",
134 "BriefDescription": "128 bit SIMD integer logical operations",
142 "BriefDescription": "128 bit SIMD integer multiply operations",
150 "BriefDescription": "128 bit SIMD integer shift operations",
158 "BriefDescription": "128 bit SIMD integer shuffle/move operations",
166 "BriefDescription": "128 bit SIMD integer unpack operations",
174 "BriefDescription": "SIMD integer 64 bit pack operations",
182 "BriefDescription": "SIMD integer 64 bit arithmetic operations",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/nehalemex/ |
| H A D | floating-point.json | 86 "BriefDescription": "Computational floating-point operations executed",
118 "BriefDescription": "128 bit SIMD integer pack operations",
126 "BriefDescription": "128 bit SIMD integer arithmetic operations",
134 "BriefDescription": "128 bit SIMD integer logical operations",
142 "BriefDescription": "128 bit SIMD integer multiply operations",
150 "BriefDescription": "128 bit SIMD integer shift operations",
158 "BriefDescription": "128 bit SIMD integer shuffle/move operations",
166 "BriefDescription": "128 bit SIMD integer unpack operations",
174 "BriefDescription": "SIMD integer 64 bit pack operations",
182 "BriefDescription": "SIMD integer 64 bit arithmetic operations",
[all …]
|