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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588j.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "rk3588-extra.dtsi"
10 cluster0_opp_table: opp-table-cluster0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1200000000 {
15 opp-hz = /bits/ 64 <1200000000>;
16 opp-microvolt = <750000 750000 950000>;
17 clock-latency-ns = <40000>;
18 opp-suspend;
[all …]
H A Drk3399-t.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 #include "rk3399-base.dtsi"
10 cluster0_opp: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
15 opp-hz = /bits/ 64 <408000000>;
16 opp-microvolt = <875000 875000 1250000>;
17 clock-latency-ns = <40000>;
20 opp-hz = /bits/ 64 <600000000>;
[all …]
H A Drk3399-op1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
9 cluster0_opp: opp-table-0 {
10 compatible = "operating-points-v2";
11 opp-shared;
14 opp-hz = /bits/ 64 <408000000>;
15 opp-microvolt = <800000 800000 1150000>;
16 clock-latency-ns = <40000>;
19 opp-hz = /bits/ 64 <600000000>;
20 opp-microvolt = <825000 825000 1150000>;
[all …]
H A Drk3588-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 cluster0_opp_table: opp-table-cluster0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-1008000000 {
9 opp-hz = /bits/ 64 <1008000000>;
10 opp-microvolt = <675000 675000 950000>;
11 clock-latency-ns = <40000>;
13 opp-1200000000 {
14 opp-hz = /bits/ 64 <1200000000>;
[all …]
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include "rk3399-base.dtsi"
9 cluster0_opp: opp-table-0 {
10 compatible = "operating-points-v2";
11 opp-shared;
14 opp-hz = /bits/ 64 <408000000>;
15 opp-microvolt = <825000 825000 1250000>;
16 clock-latency-ns = <40000>;
19 opp-hz = /bits/ 64 <600000000>;
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points)
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
[all …]
H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
25 operating-points-v2 table when it is parsed by the OPP framework.
30 - operating-points-v2-krait-cpu
31 - operating-points-v2-kryo-cpu
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-bus.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
14 operating-points-v2 = <&bus_g2d_400_opp_table>;
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
22 operating-points-v2 = <&bus_g2d_266_opp_table>;
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
30 operating-points-v2 = <&bus_gscl_opp_table>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
[all …]
H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
[all …]
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
58 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
62 cci-control-port = <&cci_control0>;
[all …]
H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
59 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
[all …]
H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
[all …]
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
28 - qcom,apq8064
29 - qcom,apq8096
30 - qcom,ipq5332
31 - qcom,ipq6018
32 - qcom,ipq8064
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm660.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
13 compatible = "qcom,adreno-512.0", "qcom,adreno";
14 operating-points-v2 = <&gpu_sdm660_opp_table>;
16 gpu_sdm660_opp_table: opp-table {
17 compatible = "operating-points-v2";
23 * at the same opp-level
25 opp-750000000 {
26 opp-hz = /bits/ 64 <750000000>;
27 opp-level = <RPM_SMD_LEVEL_TURBO>;
28 opp-peak-kBps = <5412000>;
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-khadas-vim3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 vddcpu_a: regulator-vddcpu-a {
15 compatible = "pwm-regulator";
17 regulator-name = "VDDCPU_A";
18 regulator-min-microvolt = <690000>;
19 regulator-max-microvolt = <1050000>;
21 pwm-supply = <&dc_in>;
24 pwm-dutycycle-range = <100 0>;
26 regulator-boot-on;
27 regulator-always-on;
[all …]
H A Dmeson-g12b-a311d-libretech-cc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/clock/g12a-clkc.h>
10 #include "meson-g12b-a311d.dtsi"
11 #include "meson-libretech-cottonwood.dtsi"
14 compatible = "libretech,aml-a311d-cc", "amlogic,a311d", "amlogic,g12b";
15 model = "Libre Computer AML-A311D-CC Alta";
17 vddcpu_a: regulator-vddcpu-a {
18 compatible = "pwm-regulator";
19 regulator-name = "VDDCPU_A";
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-r40-cpu-opp.dtsi2 cpu0_opp_table: opp-table-cpu {
3 compatible = "operating-points-v2";
4 opp-shared;
6 opp-720000000 {
7 opp-hz = /bits/ 64 <720000000>;
8 opp-microvolt = <1000000 1000000 1300000>;
9 clock-latency-ns = <2000000>;
12 opp-912000000 {
13 opp-hz = /bits/ 64 <912000000>;
14 opp-microvolt = <1100000 1100000 1300000>;
[all …]
/linux/Documentation/devicetree/bindings/power/
H A Dqcom,rpmpd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
19 - enum:
20 - qcom,glymur-rpmhpd
21 - qcom,mdm9607-rpmpd
22 - qcom,milos-rpmhpd
23 - qcom,msm8226-rpmpd
24 - qcom,msm8909-rpmpd
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
[all …]
H A Dtegra20-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 core_opp_table: opp-table-core {
5 compatible = "operating-points-v2";
6 opp-shared;
8 core_opp_950: opp-950000 {
9 opp-microvolt = <950000 950000 1300000>;
10 opp-level = <950000>;
13 core_opp_1000: opp-1000000 {
14 opp-microvolt = <1000000 1000000 1300000>;
15 opp-level = <1000000>;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 cpu0_opp_table: opp-table-cpu {
8 compatible = "operating-points-v2";
9 opp-shared;
11 opp-648000000 {
12 opp-hz = /bits/ 64 <648000000>;
13 opp-microvolt = <1040000>;
14 clock-latency-ns = <244144>; /* 8 32k periods */
17 opp-816000000 {
18 opp-hz = /bits/ 64 <816000000>;
[all …]
H A Dsun50i-h5-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
5 cpu_opp_table: opp-table-cpu {
6 compatible = "operating-points-v2";
7 opp-shared;
9 opp-408000000 {
10 opp-hz = /bits/ 64 <408000000>;
11 opp-microvolt = <1000000 1000000 1310000>;
12 clock-latency-ns = <244144>; /* 8 32k periods */
15 opp-648000000 {
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
16 #include "multi-die-cpp.h"
18 #include "t600x-common.dtsi"
21 compatible = "apple,t6002", "apple,arm-platform";
23 #address-cells = <2>;
[all …]
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0>; /* To be filled by loader */
69 next-level-cache = <&l2_cache_0>;
70 i-cache-size = <0x20000>;
[all …]

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