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Searched +full:ocelot +full:- +full:miim (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 ---
4 $id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ocelot Externally-Controlled Ethernet Switch
10 - Colin Foster <colin.foster@in-advantage.com>
13 The Ocelot ethernet switch family contains chips that have an internal CPU
18 The switch family is a multi-port networking switch that supports many
25 - mscc,vsc7512
30 "#address-cells":
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmscc,miim.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/mscc,miim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi MII Management Controller (MIIM)
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - $ref: mdio.yaml#
18 - mscc,ocelot-miim
19 - microchip,lan966x-miim
21 "#address-cells":
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H A Dmscc-miim.txt1 Microsemi MII Management Controller (MIIM) / MDIO
5 - compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim"
6 - reg: The base address of the MDIO bus controller register bank. Optionally, a
9 - #address-cells: Must be <1>.
10 - #size-cells: Must be <0>. MDIO addresses have no size component.
11 - interrupts: interrupt specifier (refer to the interrupt binding)
17 #address-cells = <1>;
18 #size-cells = <0>;
19 compatible = "mscc,ocelot-miim";
23 phy0: ethernet-phy@0 {
/freebsd/sys/contrib/device-tree/src/mips/mscc/
H A Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
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/freebsd/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cell
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