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Searched +full:ocelot +full:- +full:icpu +full:- +full:intr (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmscc,ocelot-icpu-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi Ocelot SoC ICPU Interrupt Controller
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 the Microsemi Ocelot interrupt controller that is part of the
17 ICPU. It is connected directly to the MIPS core interrupt
23 - enum:
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/linux/drivers/irqchip/
H A Dirq-mscc-ocelot.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot IRQ controller driver
15 #define ICPU_CFG_INTR_DST_INTR_IDENT(_p, x) ((_p)->reg_off_ident + 0x4 * (x))
16 #define ICPU_CFG_INTR_INTR_TRIGGER(_p, x) ((_p)->reg_off_trigger + 0x4 * (x))
80 struct irq_domain *d = data->domain; in ocelot_irq_unmask()
81 struct chip_props *p = d->host_data; in ocelot_irq_unmask()
83 unsigned int mask = data->mask; in ocelot_irq_unmask()
86 guard(raw_spinlock)(&gc->lock); in ocelot_irq_unmask()
96 irq_reg_writel(gc, mask, p->reg_off_sticky); in ocelot_irq_unmask()
98 *ct->mask_cache &= ~mask; in ocelot_irq_unmask()
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/linux/arch/mips/boot/dts/mscc/
H A Dluton.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
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H A Djaguar2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
29 cpuintc: interrupt-controller {
30 #address-cells = <0>;
31 #interrupt-cells = <1>;
32 interrupt-controller;
33 compatible = "mti,cpu-interrupt-controller";
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H A Dserval.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
28 cpuintc: interrupt-controller {
29 #address-cells = <0>;
30 #interrupt-cells = <1>;
31 interrupt-controller;
32 compatible = "mti,cpu-interrupt-controller";
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H A Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
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