Searched +full:ocelot +full:- +full:icpu +full:- +full:intr (Results 1 – 6 of 6) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Microsemi Ocelot SoC ICPU Interrupt Controller10 - Alexandre Belloni <alexandre.belloni@bootlin.com>13 - $ref: /schemas/interrupt-controller.yaml#16 the Microsemi Ocelot interrupt controller that is part of the17 ICPU. It is connected directly to the MIPS core interrupt23 - enum:[all …]
1 Microsemi Ocelot SoC ICPU Interrupt Controller5 - compatible : should be "mscc,ocelot-icpu-intr"6 - reg : Specifies base physical address and size of the registers.7 - interrupt-controller : Identifies the node as an interrupt controller8 - #interrupt-cells : Specifies the number of cells needed to encode an10 - interrupts : Specifies the CPU interrupt the controller is connected to.14 intc: interrupt-controller@70000070 {15 compatible = "mscc,ocelot-icpu-intr";17 #interrupt-cells = <1>;18 interrupt-controller;[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)5 #address-cells = <1>;6 #size-cells = <1>;10 #address-cells = <1>;11 #size-cells = <0>;25 cpuintc: interrupt-controller {26 #address-cells = <0>;27 #interrupt-cells = <1>;28 interrupt-controller;29 compatible = "mti,cpu-interrupt-controller";[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)7 #address-cells = <1>;8 #size-cells = <1>;18 #address-cells = <1>;19 #size-cells = <0>;29 cpuintc: interrupt-controller {30 #address-cells = <0>;31 #interrupt-cells = <1>;32 interrupt-controller;33 compatible = "mti,cpu-interrupt-controller";[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)7 #address-cells = <1>;8 #size-cells = <1>;12 #address-cells = <1>;13 #size-cells = <0>;28 cpuintc: interrupt-controller {29 #address-cells = <0>;30 #interrupt-cells = <1>;31 interrupt-controller;32 compatible = "mti,cpu-interrupt-controller";[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)5 #address-cells = <1>;6 #size-cells = <1>;7 compatible = "mscc,ocelot";10 #address-cells = <1>;11 #size-cells = <0>;25 cpuintc: interrupt-controller {26 #address-cells = <0>;27 #interrupt-cells = <1>;28 interrupt-controller;[all …]