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/freebsd/sys/contrib/device-tree/Bindings/mips/
H A Dmscc.txt7 - compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20 - reg : Should contain registers location and length
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
28 o HSIO regs:
30 The SoC has a few registers (HSIO) handling miscellaneous functionalities:
35 - compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
36 - reg : Should contain registers location and length
40 compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-ocelot-serdes.txt1 Microsemi Ocelot SerDes muxing driver
2 -------------------------------------
4 On Microsemi Ocelot, there is a handful of registers in HSIO address
13 half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
14 10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
19 This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
20 Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.
24 - compatible: should be "mscc,vsc7514-serdes"
25 - #phy-cells : from the generic phy bindings, must be 2.
28 defined in dt-bindings/phy/phy-ocelot-serdes.h
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H A Dmscc,vsc7514-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi Ocelot SerDes muxing
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - UNGLinuxDriver@microchip.com
14 On Microsemi Ocelot, there is a handful of registers in HSIO address
23 half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
24 10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
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/freebsd/sys/contrib/device-tree/src/mips/mscc/
H A Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
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