Searched +full:nwl +full:- +full:pcie +full:- +full:2 (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx NWL PCIe Root Port Bridge10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>13 - $ref: /schemas/pci/pci-host-bridge.yaml#14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#18 const: xlnx,nwl-pcie-2.1122 - description: PCIe bridge registers location.[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2014 - 2021, Xilinx, Inc.11 * published by the Free Software Foundation; either version 2 of15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>16 #include <dt-bindings/gpio/gpio.h>17 #include <dt-bindings/interrupt-controller/arm-gic.h>18 #include <dt-bindings/interrupt-controller/irq.h>19 #include <dt-bindings/power/xlnx-zynqmp-power.h>20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>21 #include <dt-bindings/thermal/thermal.h>[all …]