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/linux/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/
H A Dbase.c29 struct nvkm_nvenc *nvenc = nvkm_nvenc(engine); in nvkm_nvenc_dtor() local
30 nvkm_falcon_dtor(&nvenc->falcon); in nvkm_nvenc_dtor()
31 return nvenc; in nvkm_nvenc_dtor()
44 struct nvkm_nvenc *nvenc; in nvkm_nvenc_new_() local
47 if (!(nvenc = *pnvenc = kzalloc(sizeof(*nvenc), GFP_KERNEL))) in nvkm_nvenc_new_()
51 &nvenc->engine); in nvkm_nvenc_new_()
55 fwif = nvkm_firmware_load(&nvenc->engine.subdev, fwif, "Nvenc", nvenc); in nvkm_nvenc_new_()
59 nvenc->func = fwif->func; in nvkm_nvenc_new_()
61 return nvkm_falcon_ctor(nvenc->func->flcn, &nvenc->engine.subdev, in nvkm_nvenc_new_()
62 nvenc->engine.subdev.name, 0, &nvenc->falcon); in nvkm_nvenc_new_()
H A Dgm107.c35 gm107_nvenc_nofw(struct nvkm_nvenc *nvenc, int ver, in gm107_nvenc_nofw() argument
/linux/Documentation/devicetree/bindings/gpu/host1x/
H A Dnvidia,tegra210-nvenc.yaml4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
7 title: NVIDIA Tegra NVENC
10 NVENC is the hardware video encoder present on NVIDIA Tegra210
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
36 - const: nvenc
43 - const: nvenc
83 - nvidia,tegra210-nvenc
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Dfifo.c406 case RM_ENGINE_TYPE( NVENC0, NVENC, 0); in r535_fifo_xlat_rm_engine_type()
407 case RM_ENGINE_TYPE( NVENC1, NVENC, 1); in r535_fifo_xlat_rm_engine_type()
408 case RM_ENGINE_TYPE( NVENC2, NVENC, 2); in r535_fifo_xlat_rm_engine_type()
/linux/drivers/gpu/host1x/
H A Ddev.c151 { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 },
193 { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 },
240 { /* NVENC MMIO */ .base = 0x1690, .offset = 0x34, .limit = 0x34 },
241 { /* NVENC ch */ .base = 0x17c0, .offset = 0x30, .limit = 0x30 },
H A Dcontext.c50 * Due to an issue with T194 NVENC, only 38 bits can be used. in host1x_memory_context_list_init()
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi2090 nvenc@154c0000 {
2091 compatible = "nvidia,tegra194-nvenc";
2094 clock-names = "nvenc";
2096 reset-names = "nvenc";
2245 nvenc@15a80000 {
2246 compatible = "nvidia,tegra194-nvenc";
2249 clock-names = "nvenc";
2251 reset-names = "nvenc";
H A Dtegra186.dtsi1730 nvenc@154c0000 {
1731 compatible = "nvidia,tegra186-nvenc";
1734 clock-names = "nvenc";
1736 reset-names = "nvenc";
H A Dtegra210.dtsi283 nvenc@544c0000 {
284 compatible = "nvidia,tegra210-nvenc";
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dbase.c212 CASE(NVENC ); in nvkm_fifo_info()
/linux/include/dt-bindings/clock/
H A Dtegra186-clock.h878 /** @brief NAFLL clock source for NVENC */
H A Dtegra234-clock.h396 /** @brief NAFLL clock source for NVENC */
/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c756 MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),