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/linux/Documentation/devicetree/bindings/pci/
H A Dsamsung,exynos-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Jaehoon Chung <jh80.chung@samsung.com>
16 snps,dw-pcie.yaml.
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
23 const: samsung,exynos5433-pcie
27 - description: Data Bus Interface (DBI) registers.
[all …]
H A Dsocionext,uniphier-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
24 - socionext,uniphier-pcie
30 reg-names:
33 - const: dbi
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H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
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H A Dtoshiba,visconti-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
16 - $ref: /schemas/pci/snps,dw-pcie.yaml#
20 const: toshiba,visconti-pcie
24 - description: Data Bus Interface (DBI) registers.
25 - description: PCIe configuration space region.
26 - description: Visconti specific additional registers.
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H A Dfsl,layerscape-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
16 which is used to describe the PLL settings at the time of chip-reset.
26 - enum:
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130-crb-A.dts1 // SPDX-License-Identifier: GPL-2.0+
6 #include "cn9130-crb.dtsi"
9 model = "Marvell Armada CN9130-CRB-A";
14 num-lanes = <4>;
15 num-viewport = <8>;
21 iommu-map =
25 iommu-map-mask = <0x031f>;
30 usb-phy = <&cp0_usb3_0_phy0>;
31 phy-names = "usb";
36 usb-phy = <&cp0_usb3_0_phy1>;
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H A Dcn9130-db.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device tree for the CN9130-DB board.
10 #include <dt-bindings/gpio/gpio.h>
14 stdout-path = "serial0:115200n8";
33 ap0_reg_sd_vccq: regulator-1 {
34 compatible = "regulator-gpio";
35 regulator-name = "ap0_sd_vccq";
36 regulator-min-microvolt = <1800000>;
37 regulator-max-microvolt = <3300000>;
42 cp0_reg_usb3_vbus0: regulator-2 {
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_utils.c1 // SPDX-License-Identifier: MIT
9 *remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0); in dml2_core_utils_div_rem()
221 if (!fail_only || support->ScaleRatioAndTapsSupport == 0) in dml2_core_utils_print_mode_support_info()
222 dml2_printf("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport); in dml2_core_utils_print_mode_support_info()
223 if (!fail_only || support->SourceFormatPixelAndScanSupport == 0) in dml2_core_utils_print_mode_support_info()
224 …dml2_printf("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndS… in dml2_core_utils_print_mode_support_info()
225 if (!fail_only || support->ViewportSizeSupport == 0) in dml2_core_utils_print_mode_support_info()
226 dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport); in dml2_core_utils_print_mode_support_info()
227 if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1) in dml2_core_utils_print_mode_support_info()
228 …dml2_printf("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPV… in dml2_core_utils_print_mode_support_info()
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H A Ddml2_core_dcn4.c1 // SPDX-License-Identifier: MIT
82 ip_caps->pipe_count = ip_params->max_num_dpp; in patch_ip_caps_with_explicit_ip_params()
83 ip_caps->otg_count = ip_params->max_num_otg; in patch_ip_caps_with_explicit_ip_params()
84 ip_caps->num_dsc = ip_params->num_dsc; in patch_ip_caps_with_explicit_ip_params()
85 ip_caps->max_num_dp2p0_streams = ip_params->max_num_dp2p0_streams; in patch_ip_caps_with_explicit_ip_params()
86 ip_caps->max_num_dp2p0_outputs = ip_params->max_num_dp2p0_outputs; in patch_ip_caps_with_explicit_ip_params()
87 ip_caps->max_num_hdmi_frl_outputs = ip_params->max_num_hdmi_frl_outputs; in patch_ip_caps_with_explicit_ip_params()
88 ip_caps->rob_buffer_size_kbytes = ip_params->rob_buffer_size_kbytes; in patch_ip_caps_with_explicit_ip_params()
89 ip_caps->config_return_buffer_size_in_kbytes = ip_params->config_return_buffer_size_in_kbytes; in patch_ip_caps_with_explicit_ip_params()
90 …ip_caps->config_return_buffer_segment_size_in_kbytes = ip_params->config_return_buffer_segment_siz… in patch_ip_caps_with_explicit_ip_params()
[all …]
H A Ddml2_core_shared.c1 // SPDX-License-Identifier: MIT
13 *remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0); in dml2_core_shared_div_rem()
27 static unsigned int dml_round_to_multiple(unsigned int num, unsigned int multiple, bool up);
106 unsigned int SwathWidthY[], // per-pipe
107 unsigned int SwathWidthC[], // per-pipe
110 unsigned int swath_width_luma_ub[], // per-pipe
111 unsigned int swath_width_chroma_ub[]); // per-pipe
753 struct dml2_core_internal_display_mode_lib *mode_lib = in_out_params->mode_lib; in dml2_core_shared_mode_support()
754 const struct dml2_display_cfg *display_cfg = in_out_params->in_display_cfg; in dml2_core_shared_mode_support()
755 const struct dml2_mcg_min_clock_table *min_clk_table = in_out_params->min_clk_table; in dml2_core_shared_mode_support()
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H A Ddml2_core_dcn4_calcs.c1 // SPDX-License-Identifier: MIT
50 *remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0); in dml2_core_div_rem()
58 if (!fail_only || support->ScaleRatioAndTapsSupport == 0) in dml2_print_mode_support_info()
59 dml2_printf("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport); in dml2_print_mode_support_info()
60 if (!fail_only || support->SourceFormatPixelAndScanSupport == 0) in dml2_print_mode_support_info()
61 …dml2_printf("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndS… in dml2_print_mode_support_info()
62 if (!fail_only || support->ViewportSizeSupport == 0) in dml2_print_mode_support_info()
63 dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport); in dml2_print_mode_support_info()
64 if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1) in dml2_print_mode_support_info()
65 …dml2_printf("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPV… in dml2_print_mode_support_info()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dtransform.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
157 struct rect viewport; member
204 uint32_t num);
/linux/arch/arm64/boot/dts/toshiba/
H A Dtmpv7708.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
50 DPP_CLOCK_ENABLE, &s->is_enabled); in dpp30_read_state()
52 // Pre-degamma (ROM) in dpp30_read_state()
54 PRE_DEGAM_MODE, &s->pre_dgam_mode, in dpp30_read_state()
55 PRE_DEGAM_SELECT, &s->pre_dgam_select); in dpp30_read_state()
59 CM_GAMCOR_MODE_CURRENT, &s->gamcor_mode); in dpp30_read_state()
60 if (s->gamcor_mode) { in dpp30_read_state()
63 s->gamcor_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B in dpp30_read_state()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
H A Ddml_top_display_cfg_types.h1 // SPDX-License-Identifier: MIT
221 } viewport; member
259 // for dv to specify num dsc slices to use
318 * RGB or YUV Non-Planar Types:
328 * YUV Planar-Types:
342 * Mono Non-Planar Types:
384 … the corresponding stream in mode_programming would be at least as much as this per-plane override.
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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/linux/include/uapi/drm/
H A Dradeon_drm.h1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
66 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
72 /* New style per-packet identifiers for use in cmd_buffer ioctl with
84 #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
183 #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
234 /* these two defines are DOING IT WRONG - however
332 * a 1K-byte boundary.
336 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
384 /* Viewport state */
450 /* Counters for client-side throttling of rendering clients.
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c66 hws->ctx
68 hws->regs->reg
72 hws->shifts->field_name, hws->masks->field_name
77 struct dc_context *dc_ctx = dc->ctx; in dcn20_log_color_state()
78 struct resource_pool *pool = dc->res_pool; in dcn20_log_color_state()
87 for (i = 0; i < pool->pipe_count; i++) { in dcn20_log_color_state()
88 struct dpp *dpp = pool->dpps[i]; in dcn20_log_color_state()
91 dpp->funcs->dpp_read_state(dpp, &s); in dcn20_log_color_state()
92 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); in dcn20_log_color_state()
101 dpp->inst, in dcn20_log_color_state()
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