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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - xlnx,xps-spi-2.00.a
19 - xlnx,xps-spi-2.00.b
20 - xlnx,axi-quad-spi-1.00.a
28 xlnx,num-ss-bits:
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/linux/sound/core/
H A Dpcm_lib.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Abramo Bagnara <abramo@alsa-project.org>
43 delta = new_ptr - ptr; in update_silence_vars()
47 delta += runtime->boundary; in update_silence_vars()
48 if ((snd_pcm_uframes_t)delta < runtime->silence_filled) in update_silence_vars()
49 runtime->silence_filled -= delta; in update_silence_vars()
51 runtime->silence_filled = 0; in update_silence_vars()
52 runtime->silence_start = new_ptr; in update_silence_vars()
57 * runtime->silence_start: starting pointer to silence area
58 * runtime->silence_filled: size filled with silence
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/linux/drivers/media/common/saa7146/
H A Dsaa7146_i2c.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <media/drv-intf/saa7146_vv.h>
8 /* DEB_I2C("'%s'\n", adapter->name); */ in saa7146_i2c_func()
16 /* this function returns the status-register of our i2c-device */
24 /* this function runs through the i2c-messages and prepares the data to be
26 to understand this. it returns the number of u32s to send, or -1
28 static int saa7146_i2c_msg_prepare(const struct i2c_msg *m, int num, __le32 *op) in saa7146_i2c_msg_prepare() argument
35 for(i = 0; i < num; i++) { in saa7146_i2c_msg_prepare()
41 mem = 1 + ((mem-1) / 3); in saa7146_i2c_msg_prepare()
47 /* DEB_I2C("cannot prepare i2c-message\n"); */ in saa7146_i2c_msg_prepare()
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/linux/drivers/usb/gadget/udc/bdc/
H A Dbdc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * bdc.h - header for the BRCM BDC USB3.0 device controller
18 #include <linux/dma-mapping.h>
46 /* Num of bds per table */
49 /* Num of tables in bd list for control,bulk and Int ep */
52 /* Num of tables in bd list for Isoch ep */
223 /* Control transfer BD specific fields */
242 /* Transfer BD fields */
252 /* One BD can transfer max 65536 bytes */
274 /* On disconnect, preserve these bits and clear rest */
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
28 * 1 byte takes 9 clock cycles (8 bits + 1 ACK) = 90 us for 100 kHz in fifo_transfer()
41 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); in fifo_transfer()
44 * Limit transfer length by FIFO threshold or FIFO size. in fifo_transfer()
49 /* Wait until error, FIFO request bit set or transfer complete */ in fifo_transfer()
50 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, in fifo_transfer()
53 return -ETIMEDOUT; in fifo_transfer()
56 return -EIO; in fifo_transfer()
59 ioread8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
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/linux/drivers/message/fusion/
H A Dmptctl.h8 * Copyright (c) 1999-2008 LSI Corporation
9 * (mailto:DL-MPTFusionLinux@lsi.com)
12 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
50 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
54 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
93 * (as the app. will not use 8-byte pointers).
117 * iocnum - must be defined.
118 * port - must be defined for all IOCTL commands other than MPTIOCINFO
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/linux/drivers/mmc/core/
H A Dsdio_io.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Pierre Ossman
21 * sdio_claim_host - exclusively claim a bus for a certain SDIO function
32 mmc_claim_host(func->card->host); in sdio_claim_host()
37 * sdio_release_host - release a bus for a certain SDIO function
48 mmc_release_host(func->card->host); in sdio_release_host()
53 * sdio_enable_func - enables a SDIO function for usage
66 return -EINVAL; in sdio_enable_func()
70 ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IOEx, 0, &reg); in sdio_enable_func()
74 reg |= 1 << func->num; in sdio_enable_func()
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/linux/drivers/i2c/busses/
H A Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
36 #define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer
39 #define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
76 /* calculate the value of CS bits in CCR register on standard mode */
78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
81 /* calculate the value of CS bits in CSR register on standard mode */
84 /* calculate the value of CS bits in CCR register on fast mode */
86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
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H A Di2c-qup.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
125 /* Maximum transfer length for single DMA descriptor */
128 /* Maximum transfer length for all DMA descriptors */
133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
134 * the top of maximum transfer time calculated from i2c bus speed to compensate
145 * data transfer
164 * total_tx_len: total tx length including tag bytes for current QUP transfer
165 * total_rx_len: total rx length including tag bytes for current QUP transfer
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H A Di2c-pnx.c7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
82 #define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
83 #define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
84 #define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
85 #define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
86 #define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
87 #define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
88 #define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
89 #define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
90 #define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
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H A Di2c-hisi.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/bits.h>
97 /* Intermediates for recording the transfer process */
116 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_enable_int()
121 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_disable_int()
126 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); in hisi_i2c_clear_int()
131 writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR); in hisi_i2c_clear_tx_int()
136 u32 int_err = ctlr->xfer_err, reg; in hisi_i2c_handle_errors()
139 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_handle_errors()
142 dev_err(ctlr->dev, "rx fifo error read\n"); in hisi_i2c_handle_errors()
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H A Di2c-mchp-pci1xxxx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2021 - 2022 Microchip Technology Inc.
12 #include <linux/bits.h>
15 #include <linux/i2c-smbus.h>
143 * START bit in a transfer.
198 * CTRL_CUM_TIME_OUT_XK_TICKS defines SMBus Controller Cumulative Time-Out.
199 * SMBus Controller Cumulative Time-Out duration =
207 * TARGET_CUM_TIME_OUT_XK_TICKS defines SMBus Target Cumulative Time-Out duration.
208 * SMBus Target Cumulative Time-Out duration = TARGET_CUM_TIME_OUT_XK_TICKS[7:0] x
336 void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG; in set_sys_lock()
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/linux/drivers/usb/gadget/udc/cdns2/
H A Dcdns2-gadget.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence USBHS-DEV Driver - gadget side.
28 #include <linux/dma-mapping.h>
36 #include "cdns2-gadget.h"
37 #include "cdns2-trace.h"
40 * set_reg_bit_32 - set bit in given 32 bits registe
1931 unsigned long num; cdns2_find_available_ep() local
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/linux/Documentation/devicetree/bindings/mailbox/
H A Darm,mhu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
24 check the status of each of the bits of this register independently. The use
25 of 32 bits per interrupt line enables software to provide more information
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
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/linux/drivers/gpu/drm/
H A Ddrm_mipi_dbi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
62 * 1. 9-bit with the Data/Command signal as the ninth bit
63 * 2. Same as above except it's sent as 16 bits
64 * 3. 8-bit with the Data/Command signal as a separate D/CX pin
108 if (!dbi->read_commands) in mipi_dbi_command_is_read()
112 if (!dbi->read_commands[i]) in mipi_dbi_command_is_read()
114 if (cmd == dbi->read_commands[i]) in mipi_dbi_command_is_read()
122 * mipi_dbi_command_read - MIPI DCS read command
134 if (!dbi->read_commands) in mipi_dbi_command_read()
135 return -EACCES; in mipi_dbi_command_read()
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/linux/drivers/iio/adc/
H A Dti-adc084s021.c1 // SPDX-License-Identifier: GPL-2.0-only
36 * transfer buffers to live in their own cache line.
39 __be16 rx_buf[5]; /* First 16-bits are trash */
42 #define ADC084S021_VOLTAGE_CHANNEL(num) \ argument
45 .channel = (num), \
47 .scan_index = (num), \
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/linux/drivers/media/platform/ti/vpe/
H A Dvpdma.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
26 #define VPDMA_FIRMWARE "vpdma-1b8.bin"
197 * To handle RAW format we are re-using the CBY422
198 * vpdma data type so that we use the vpdma to re-order
202 * RAW8 handles from 1 to 8 bits
203 * RAW16 handles from 9 to 16 bits
229 int num; /* VPDMA channel number */ member
235 .num = VPE_CHAN_NUM_LUMA1_IN,
239 .num = VPE_CHAN_NUM_CHROMA1_IN,
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/linux/drivers/media/pci/cobalt/
H A Dcobalt-i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Derived from cx18-i2c.c
7 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include "cobalt-driver.h"
12 #include "cobalt-i2c.h"
15 /* Clock prescaler register lo-byte */
18 /* Clock prescaler register high-byte */
32 /* CTR[7:0] - Control register */
40 /* CR[7:0] - Command register */
60 /* SR[7:0] - Status register */
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/linux/drivers/net/ethernet/sun/
H A Dsunqe.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
40 * status bits in the QEC status register. This macro picks out the
45 /* The following registers are for per-qe channel information/status. */
59 #define CREG_PIPG 0x34UL /* Inter-Frame Gap */
74 #define CREG_STAT_CCOFLOW 0x00100000 /* TX Coll-counter Overflow */
79 #define CREG_STAT_RCCOFLOW 0x00001000 /* RX Coll-counter Overflow */
85 #define CREG_STAT_CECOFLOW 0x00000040 /* CRC Error-counter Overflow*/
121 #define CREG_MMASK_RXCOLL 0x00000400 /* RX Coll-Cntr overflow */
129 /* Per-channel AMD 79C940 MACE registers. */
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/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxilinx_dma.txt11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
24 - #dma-cells: Should be <1>, see "dmas" property below
25 - reg: Should contain VDMA registers location and length.
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/linux/drivers/spi/
H A Dspi-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/dma-mapping.h>
22 #include <linux/platform_data/spi-davinci.h>
136 if (dspi->rx) { in davinci_spi_rx_buf_u8()
137 u8 *rx = dspi->rx; in davinci_spi_rx_buf_u8()
139 dspi->rx = rx; in davinci_spi_rx_buf_u8()
145 if (dspi->rx) { in davinci_spi_rx_buf_u16()
146 u16 *rx = dspi->rx; in davinci_spi_rx_buf_u16()
148 dspi->rx = rx; in davinci_spi_rx_buf_u16()
156 if (dspi->tx) { in davinci_spi_tx_buf_u8()
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H A Dspi-hisi-kunpeng.c1 // SPDX-License-Identifier: GPL-2.0-only
8 // This code is based on spi-dw-core.c.
49 /* Bit fields in HISI_SPI_IMR, 4 bits */
56 /* Bit fields in HISI_SPI_SR, 5 bits */
63 /* Bit fields in HISI_SPI_ISR, 4 bits */
70 /* Bit fields in HISI_SPI_ICR, 2 bits */
131 /* Current message transfer state info */
167 host = container_of(hs->dev, struct spi_controller, dev); in hisi_spi_debugfs_init()
168 snprintf(name, 32, "hisi_spi%d", host->bus_num); in hisi_spi_debugfs_init()
169 hs->debugfs = debugfs_create_dir(name, NULL); in hisi_spi_debugfs_init()
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H A Dspi-armada-3700.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Armada-3700 SPI controller driver
8 * Author: Romain Perier <romain.perier@free-electrons.com>
118 return readl(a3700_spi->base + offset); in spireg_read()
123 writel(data, a3700_spi->base + offset); in spireg_write()
171 /* RX during address reception uses 4-pin */ in a3700_spi_pin_mode_set()
176 dev_err(&a3700_spi->host->dev, "wrong pin mode %u", pin_mode); in a3700_spi_pin_mode_set()
177 return -EINVAL; in a3700_spi_pin_mode_set()
223 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); in a3700_spi_clock_set()
256 a3700_spi->byte_len = len; in a3700_spi_bytelen_set()
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/linux/drivers/scsi/megaraid/
H A Dmbox_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (c) 2003-2004 LSI Logic Corporation.
137 * struct mbox_t - Driver and f/w handshake structure.
142 * @xferaddr : DMA address for data transfer
154 * structure must be allocated by the driver and aligned at 8-byte boundary.
176 * mbox64_t - 64-bit extension for the mailbox
177 * @segment_lo : the low 32-bits of the address of the scatter-gather list
178 * @segment_hi : the upper 32-bits of the address of the scatter-gather list
179 * @mbox : 32-bit mailbox, whose xferadder field must be set to
182 * This is the extension of the 32-bit mailbox to be able to perform DMA
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/linux/drivers/scsi/
H A Desp_scsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */
12 #define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */
13 #define ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */
14 #define ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */
20 #define ESP_STP ESP_SSTEP /* wo Transfer period/sync 0x18 */
21 #define ESP_FFLAGS 0x07UL /* ro Bits current FIFO info 0x1c */
30 #define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */
40 /* ESP config reg 1, read-write, found on all ESP chips */
41 #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
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