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/linux/drivers/leds/flash/
H A Dleds-mt6370-flash.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/led-class-flash.h>
22 #include <media/v4l2-flash-led-class.h>
43 #define MT6370_FLCSEN_MASK(_id) BIT(MT6370_LED_FLASH2 - (_id))
90 struct mt6370_priv *priv = led->priv; in mt6370_torch_brightness_set()
91 u32 led_enable_mask = led->led_no == MT6370_LED_JOINT ? MT6370_FLCSEN_MASK_ALL : in mt6370_torch_brightness_set()
92 MT6370_FLCSEN_MASK(led->led_no); in mt6370_torch_brightness_set()
98 mutex_lock(&priv->lock); in mt6370_torch_brightness_set()
104 if (priv->fled_strobe_used) { in mt6370_torch_brightness_set()
105 dev_warn(lcdev->dev, "Please disable strobe first [%d]\n", priv->fled_strobe_used); in mt6370_torch_brightness_set()
[all …]
H A Dleds-sy7802.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/led-class-flash.h>
112 struct sy7802 *chip = led->chip; in sy7802_torch_brightness_set()
120 mutex_lock(&chip->mutex); in sy7802_torch_brightness_set()
122 if (chip->fled_strobe_used) { in sy7802_torch_brightness_set()
123 dev_warn(chip->dev, "Cannot set torch brightness whilst strobe is enabled\n"); in sy7802_torch_brightness_set()
124 ret = -EBUSY; in sy7802_torch_brightness_set()
129 fled_torch_used_tmp = chip->fled_torch_used | BIT(led->led_id); in sy7802_torch_brightness_set()
131 fled_torch_used_tmp = chip->fled_torch_used & ~BIT(led->led_id); in sy7802_torch_brightness_set()
133 led_enable_mask = led->led_id == SY7802_LED_JOINT ? in sy7802_torch_brightness_set()
[all …]
/linux/Documentation/devicetree/bindings/nios2/
H A Dnios2.txt6 Users can use sopc2dts tool for generating device tree sources (dts) from a
11 - compatible: Compatible property value should be "altr,nios2-1.0".
12 - reg: Contains CPU index.
13 - interrupt-controller: Specifies that the node is an interrupt controller
14 - #interrupt-cells: Specifies the number of cells needed to encode an
16 - clock-frequency: Contains the clock frequency for CPU, in Hz.
17 - dcache-line-size: Contains data cache line size.
18 - icache-line-size: Contains instruction line size.
19 - dcache-size: Contains data cache size.
20 - icache-size: Contains instruction cache size.
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/linux/drivers/firmware/imx/
H A Dsm-misc.c1 // SPDX-License-Identifier: GPL-2.0+
20 return -EPROBE_DEFER; in scmi_imx_misc_ctrl_set()
22 return imx_misc_ctrl_ops->misc_ctrl_set(ph, id, 1, &val); in scmi_imx_misc_ctrl_set()
26 int scmi_imx_misc_ctrl_get(u32 id, u32 *num, u32 *val) in scmi_imx_misc_ctrl_get() argument
29 return -EPROBE_DEFER; in scmi_imx_misc_ctrl_get()
31 return imx_misc_ctrl_ops->misc_ctrl_get(ph, id, num, val); in scmi_imx_misc_ctrl_get()
49 const struct scmi_handle *handle = sdev->handle; in scmi_imx_misc_ctrl_probe()
50 struct device_node *np = sdev->dev.of_node; in scmi_imx_misc_ctrl_probe()
52 int ret, i, num; in scmi_imx_misc_ctrl_probe() local
55 return -ENODEV; in scmi_imx_misc_ctrl_probe()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-droid4-xt894.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include "motorola-mapphone-xt8xx.dtsi"
11 stdout-path = &uart3;
20 compatible = "gpio-keys";
26 linux,can-disable;
28 debounce-interval = <10>;
37 interrupts-extended = <&omap4_pmx_core 0xd6>;
39 linux,input-type = <EV_SW>;
41 linux,can-disable;
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H A Domap4-droid-bionic-xt875.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include "motorola-mapphone-xt8xx.dtsi"
8 compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4";
11 stdout-path = &uart3;
21 keypad,num-rows = <8>;
22 keypad,num-columns = <8>;
30 led-controller@38 {
32 #address-cells = <1>;
33 #size-cells = <0>;
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/linux/drivers/irqchip/
H A Dirq-riscv-aplic-main.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/irqchip/riscv-aplic.h>
10 #include <linux/irqchip/riscv-imsic.h>
17 #include "irq-riscv-aplic-main.h"
23 writel(d->hwirq, priv->regs + APLIC_SETIENUM); in aplic_irq_unmask()
30 writel(d->hwirq, priv->regs + APLIC_CLRIENUM); in aplic_irq_mask()
56 return -EINVAL; in aplic_irq_set_type()
59 sourcecfg = priv->regs + APLIC_SOURCECFG_BASE; in aplic_irq_set_type()
60 sourcecfg += (d->hwirq - 1) * sizeof(u32); in aplic_irq_set_type()
69 if (WARN_ON(fwspec->param_count < 2)) in aplic_irqdomain_translate()
[all …]
H A Dirq-imgpdc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2010-2013 Imagination Technologies Ltd.
66 * struct pdc_intc_priv - private pdc interrupt data.
92 iowrite32(data, priv->pdc_base + reg_offs); in pdc_write()
98 return ioread32(priv->pdc_base + reg_offs); in pdc_read()
112 return hw - SYS0_HWIRQ; in hwirq_to_syswake()
122 return (struct pdc_intc_priv *)data->domain->host_data; in irqd_to_priv()
135 raw_spin_lock(&priv->lock); in perip_irq_mask()
136 priv->irq_route &= ~data->mask; in perip_irq_mask()
137 pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); in perip_irq_mask()
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/linux/drivers/usb/gadget/function/
H A Df_sourcesink.c1 // SPDX-License-Identifier: GPL-2.0+
3 * f_sourcesink.c - USB peripheral source/sink configuration driver
5 * Copyright (C) 2003-2008 David Brownell
25 * This just sinks bulk packets OUT to the peripheral and sources them IN
30 * plus two that support control-OUT tests. If the optional "autoresume"
32 * test harness from USB-IF.
58 /*-------------------------------------------------------------------------*/
271 /* function-specific strings: */
279 .language = 0x0409, /* en-us */
288 /*-------------------------------------------------------------------------*/
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/linux/tools/include/nolibc/
H A Darch-mips.h1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
4 * Copyright (C) 2017-2022 Willy Tarreau <w@1wt.eu>
18 * - WARNING! there's always a delayed slot!
19 * - WARNING again, the syntax is different, registers take a '$' and numbers
21 * - registers are 32-bit
22 * - stack is 8-byte aligned
23 * - syscall number is passed in v0 (starts at 0xfa0).
24 * - arguments are in a0, a1, a2, a3, then the stack. The caller needs to
26 * - Many registers are clobbered, in fact only a0..a2 and s0..s8 are
27 * preserved. See: https://www.linux-mips.org/wiki/Syscall as well as
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/linux/Documentation/devicetree/bindings/net/
H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
28 appropriate programming of the rx and tx interrupt sources on the appropriate
35 lines can also be routed to different processor sub-systems on DRA7xx as they
49 within a SoC. The sub-mailboxes (actual communication channels) are
56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
59 phandle to the intended sub-mailbox child node to be used for communication.
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5341.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mike Looijmans <mike.looijmans@topic.nl>
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
25 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
33 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
42 - silabs,si5340
[all …]
/linux/sound/firewire/bebob/
H A Dbebob_focusrite.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bebob_focusrite.c - a part of driver for BeBoB based devices
5 * Copyright (c) 2013-2014 Takashi Sakamoto
29 /* clock sources as returned from register of Saffire Pro 10 and 26 */
68 err = snd_fw_transaction(bebob->unit, TCODE_READ_BLOCK_REQUEST, in saffire_read_block()
86 err = snd_fw_transaction(bebob->unit, TCODE_READ_QUADLET_REQUEST, in saffire_read_quad()
102 return snd_fw_transaction(bebob->unit, TCODE_WRITE_QUADLET_REQUEST, in saffire_write_quad()
124 [SAFFIREPRO_CLOCK_SOURCE_SKIP] = -1, /* not supported */
126 [SAFFIREPRO_CLOCK_SOURCE_ADAT1] = -1, /* not supported */
127 [SAFFIREPRO_CLOCK_SOURCE_ADAT2] = -1, /* not supported */
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm4708-buffalo-wzr-1750dhp.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 * DTS for Buffalo WZR-1750DHP
9 /dts-v1/;
12 #include "bcm5301x-nand-cs0-bch8.dtsi"
15 compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708";
16 model = "Buffalo WZR-1750DHP (BCM4708)";
29 compatible = "spi-gpio";
30 num-chipselects = <1>;
31 sck-gpios = <&chipcommon 7 0>;
32 mosi-gpios = <&chipcommon 4 0>;
[all …]
H A Dbcm4708-buffalo-wzr-1166dhp-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 * DTS for Buffalo WZR-1166DHP and WZR-1166DHP2
12 #include "bcm5301x-nand-cs0-bch8.dtsi"
13 #include <dt-bindings/leds/common.h>
17 compatible = "spi-gpio";
18 num-chipselects = <1>;
19 sck-gpios = <&chipcommon 7 0>;
20 mosi-gpios = <&chipcommon 4 0>;
21 cs-gpios = <&chipcommon 6 0>;
22 #address-cells = <1>;
[all …]
/linux/sound/core/seq/
H A Dseq_ports.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
31 struct list_head src_list; /* link of sources */
90 struct snd_seq_client_port *snd_seq_port_use_ptr(struct snd_seq_client *client, int num);
92 /* search for next port - port is locked if found */
97 #define snd_seq_port_unlock(port) snd_use_lock_free(&(port)->use_lock)
/linux/tools/testing/selftests/bpf/
H A DREADME.rst7 __ /Documentation/bpf/bpf_devel_QA.rst#q-how-to-run-bpf-selftests
31 trampoline support on IBM's s390x architecture. For cases like this, an in-tree
45 This last entry helps identify tests that can be re-enabled once such support is
54 would be run post-submit in the CI used by the Maintainers, with the exception
57 This script uses the in-tree kernel configuration and downloads a VM userspace
64 - clang (preferably built from sources, https://github.com/llvm/llvm-project);
65 - pahole (preferably built from sources, https://git.kernel.org/pub/scm/devel/pahole/pahole.git/);
66 - qemu;
67 - docutils (for ``rst2man``);
68 - libcap-devel.
[all …]
/linux/Documentation/driver-api/
H A Dvme.rst5 -------------------
24 .. code-block:: c
30 if (vdev->id.num >= USER_BUS_MAX)
39 Here, the 'num' field refers to the sequential device ID for this specific
41 dev->bridge->num.
49 -------------------
53 succeeds, a non-zero value should be returned. A zero return value indicates
73 transfers to be provided in the route attributes. This is typically VME-to-MEM
74 and/or MEM-to-VME, though some hardware can support VME-to-VME and MEM-to-MEM
85 --------------
[all …]
/linux/drivers/soc/fsl/qbman/
H A Dbman.c1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
39 /* Cache-inhibited register offsets */
50 /* Cache-enabled register offsets */
59 /* Cache-inhibited register offsets */
70 /* Cache-enabled register offsets */
86 * ci == cache-inhibited portal register
87 * ce == cache-enabled portal register
88 * vb == in-band valid-bit (cache-enabled)
91 bm_rcr_pci = 0, /* PI index, cache-inhibited */
92 bm_rcr_pce = 1, /* PI index, cache-enabled */
[all …]
/linux/include/linux/mfd/
H A Ddbx500-prcmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
40 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
41 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
42 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
43 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
44 * - EPOD_ID_SGA: power domain for SGA
45 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
46 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
47 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
[all …]
/linux/drivers/media/usb/pvrusb2/
H A Dpvrusb2-i2c-core.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <media/i2c/ir-kbd-i2c.h>
10 #include "pvrusb2-i2c-core.h"
11 #include "pvrusb2-hdw-internal.h"
12 #include "pvrusb2-debug.h"
13 #include "pvrusb2-fx2-cmd.h"
29 static int ir_mode[PVR_NUM] = { [0 ... PVR_NUM-1] = 1 };
44 /* Return value - default 0 means success */ in pvr2_i2c_write()
49 if (length > (sizeof(hdw->cmd_buffer) - 3)) { in pvr2_i2c_write()
53 length,(unsigned int)(sizeof(hdw->cmd_buffer) - 3)); in pvr2_i2c_write()
[all …]
/linux/drivers/gpu/ipu-v3/
H A Dipu-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
26 #include <video/imx-ipu-v3.h>
27 #include "ipu-prv.h"
31 return readl(ipu->cm_reg + offset); in ipu_cm_read()
36 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
41 return ipu->id; in ipu_get_num()
157 return -EINVAL; in ipu_degrees_to_rot_mode()
168 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) in ipu_idmac_get() argument
172 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
[all …]
/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h8 * Copyright (C) 1999-2006 Tensilica Inc.
25 /*----------------------------------------------------------------------
27 ----------------------------------------------------------------------*/
29 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
31 #define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
35 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
45 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
59 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
67 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
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