Home
last modified time | relevance | path

Searched +full:num +full:- +full:ob +full:- +full:windows (Results 1 – 25 of 30) sorted by relevance

12

/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-lx2160a-rev2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
12 compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
15 reg-names = "regs", "config";
21 interrupt-names = "intr";
23 /delete-property/ apio-wins;
24 /delete-property/ ppio-wins;
28 compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
31 reg-names = "regs", "config";
[all …]
H A Dimx8-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
9 hsio_axi_clk: clock-hsio-axi {
10 compatible = "fixed-clock";
11 #clock-cells = <0>;
12 clock-frequency = <400000000>;
13 clock-output-names = "hsio_axi_clk";
16 hsio_per_clk: clock-hsio-per {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
H A Dimx8qm-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 compatible = "fsl,imx8q-pcie";
19 reg-names = "dbi", "config";
22 #interrupt-cells = <1>;
24 interrupt-names = "msi";
25 #address-cells = <3>;
26 #size-cells = <2>;
[all …]
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
[all …]
H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
[all …]
H A Dimx8mm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Ddesignware-pcie.txt4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
19 - #interrupt-cells: set to <1>
[all …]
H A Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
22 - socionext,uniphier-nx1-pcie-ep
28 reg-names:
31 - const: dbi
[all …]
H A Dpci-keystone.txt6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
24 (required if the compatible is "ti,keystone-pcie")
25 msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
[all …]
H A Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../snps,dw-pcie.yaml
[all …]
H A Dfsl,imx6q-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
23 - fsl,imx8mq-pcie-ep
24 - fsl,imx8mp-pcie-ep
[all …]
H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
[all …]
H A Dnvidia,tegra194-pcie.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
5 snps,dw-pcie-ep.yaml.
10 - power-domains: A phandle to the node that controls power to the respective
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
26 "config": As per the definition in snps,dw-pcie.yaml
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
33 entry for each entry in the interrupt-names property.
[all …]
/freebsd/contrib/less/
H A Doutput.c2 * Copyright (C) 1984-2025 Mark Nudelman
17 #include "windows.h"
85 * win_flush has at least one non-critical issue when an escape sequence
87 * as a temporary measure to reduce likelyhood of encountering end-of-buffer
88 * issues till the SGR parser is replaced, OUTBUF_SIZE is 8K on Windows.
91 static char *ob = obuf; variable
109 #define T_ANSI 1ul /* colors 0-7 */
125 /* returns 0 on success, non-0 on unknown SGR code */
132 case 1: sgr->attr |= A_BOLD; break; in update_sgr()
133 case 22: sgr->attr &= ~A_BOLD; break; in update_sgr()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3568-nanopi-r5s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
10 #include "rk3568-nanopi-r5s.dtsi"
14 compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
20 gpio-keys {
21 compatible = "gpio-keys";
22 pinctrl-0 = <&gpio4_a0_k1_pin>;
23 pinctrl-names = "default";
25 button-reset {
26 debounce-interval = <50>;
[all …]
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
[all …]
H A Drk3576.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rk3576-power.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
18 interrupt-parent = <&gic>;
[all …]
H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rockchip,rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
/freebsd/sys/contrib/device-tree/src/arm/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/socionext/
H A Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 enable-method = "psci";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
/freebsd/contrib/bc/src/
H A Dprogram.c4 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright (c) 2018-2025 Gavin D. Howard and contributors.
62 assert(r->t != BC_RESULT_VOID); in bc_program_type_num()
79 if (BC_ERR((r->t != BC_RESULT_ARRAY) != (!t))) bc_err(BC_ERR_EXEC_TYPE); in bc_program_type_match()
86 * see the development manual (manuals/development.md#bytecode-indices).
116 return *((char**) bc_vec_item(&p->strs, n->scale)); in bc_program_string()
134 bc_vec_push(p->globals_v + i, p->globals + i); in bc_program_prepGlobals()
138 bc_rand_push(&p->rng); in bc_program_prepGlobals()
158 BcVec* v = p->globals_v + i; in bc_program_popGlobals()
159 bc_vec_npop(v, reset ? v->len - 1 : 1); in bc_program_popGlobals()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
20 interrupt-parent = <&crossbar_mpu>;
47 compatible = "arm,armv7-timer";
[all …]

12