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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIDefines.h1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 //===----------------------------------------------------------------------===//
28 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1,
54 // Low bits - basic encoding information.
100 // High bits - other information.
181 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
199 /// Operands with register or 32-bit immediate
233 /// Operand with 32-bit immediate that uses the constant bus.
283 // Input operand modifiers bit-masks
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H A DAMDGPUGlobalISelDivergenceLowering.cpp1 //===-- AMDGPUGlobalISelDivergenceLowering.cpp ----------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 /// Handles all cases of temporal divergence.
13 /// For divergent non-phi i1 and uniform i1 uses outside of the cycle this pass
16 //===----------------------------------------------------------------------===//
25 #define DEBUG_TYPE "amdgpu-global-isel-divergence-lowering"
88 // _(s1) -> SReg_32/64(s1)
90 assert(MRI->getType(DstReg) == LLT::scalar(1)); in markAsLaneMask()
92 if (MRI->getRegClassOrNull(DstReg)) { in markAsLaneMask()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DLoopCacheAnalysis.h1 //===- llvm/Analysis/LoopCacheAnalysis.h ---------
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DLoopCacheAnalysis.cpp1 //===- LoopCacheAnalysis.cpp - Loop Cache Analysis -------------------------==//
7 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9 //===----------------------------------------------------------------------===//
16 /// By: Steve Carr, Katherine S. McKinley, Chau-Wen Tseng
17 /// http://www.cs.utexas.edu/users/mckinley/papers/asplos-1994.pdf
21 /// 1. Partition memory references that exhibit temporal or spacial reuse
26 //===----------------------------------------------------------------------===//
43 #define DEBUG_TYPE "loop-cache-cost"
46 "default-trip-count", cl::init(100), cl::Hidden,
49 // In this analysis two array references are considered to exhibit temporal
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/freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/
H A Dcache.json22 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
37 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac…
193 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
205 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
217 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
641 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th…
649 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t…
654 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th…
662 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t…
667 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th…
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/freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A Dcache.json26 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
45 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac…
216 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
229 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
242 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
791 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th…
801 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t…
806 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th…
816 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t…
821 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th…
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dclzerointrin.h1 /*===----------------------- clzerointrin.h - CLZERO ----------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
21 /// non-temporal store. Calling \c _mm_sfence() afterward might be needed
/freebsd/lib/libc/nls/
H A Dgl_ES.ISO8859-1.msg2 $ Message catalog for gl_ES.ISO8859-1 locale
8 1 Operaci�n non permitida
18 6 Dispositivo non configurado
26 10 Non hai procesos fillos
30 12 Non se puido asignar memoria
46 20 Non � un directorio
62 28 Non queda espacio libre no dispositivo
76 35 O recurso non est� dispo�ible temporalmente
90 42 Protocolo non dispo�ible
92 43 Protocolo non contemplado
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/freebsd/contrib/ofed/include/
H A Dudma_barrier.h14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
41 are looking for barriers to use with cache-coherent multi-threaded
47 - CPU attached address space (the CPU memory could be a range of things:
48 cached/uncached/non-temporal CPU DRAM, uncached MMIO space in another
53 - A DMA initiator on a bus. For instance a PCI-E device issuing
57 happens if a MemRd TLP is sent in via PCI-E relative to a CPU WRITE to the
80 memory types or non-temporal stores are required to use SFENCE in their own
117 from the device - eg by reading a MMIO register or seeing that CPU memory is
167 wqe->addr = ...;
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/freebsd/contrib/llvm-project/llvm/include/llvm/ProfileData/
H A DInstrProfReader.h1 //===- InstrProfReader.h - Instrumented profiling readers -------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
64 if (Error E = Reader->readNextRecord(Record)) { in increment()
86 value_type *operator->() { return &Record; }
135 /// Return true if this has a temporal profile.
144 /// of readers are used only by llvm-profdata tool, while the indexed
145 /// profile reader is also used by llvm-cov tool and the compiler (
150 /// only used for dumping purpose with llvm-proftool, not with the
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H A DInstrProf.h1 //===- InstrProf.h - Instrumented profiling format support ------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Instrumentation-based profiling data is generated by instrumented
10 // binaries through library functions in compiler-rt, and read by the clang
13 //===----------------------------------------------------------------------===//
67 return std::numeric_limits<uint64_t>::max() - 2; in getInstrMaxCountValue()
97 /// Return the name prefix of variables containing per-function control data.
133 /// Return the name of function that registers all the per-function control
142 /// Return the name of the runtime interface that registers per-function control
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/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DRedeclarable.h1 //===- Redeclarable.h - Base for Decls that can be redeclared --*- C++ -*-====//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
32 // - Every redeclarable is on a circular linked list.
34 // - Every decl has a pointer to the first element of the chain _and_ a
36 // - the "previous" (temporal) element in the chain
37 // - the "latest" (temporal) element in the chain
38 // - the "uninitialized-latest" value (when newly-constructed)
40 // - The first element is also often called the canonical element. Every
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/freebsd/contrib/wpa/wpa_supplicant/doc/docbook/
H A Dwpa_background.sgml1 <!doctype refentry PUBLIC "-//OASIS//DTD DocBook V4.1//EN">
14 <refpurpose>Background information on Wi-Fi Protected Access and IEEE 802.11i</refpurpose>
28 <para>Wi-Fi Alliance (http://www.wi-fi.org/) used a draft version
31 hardware. This is called Wi-Fi Protected Access&lt;TM&gt; (WPA). This
33 and certification done by Wi-Fi Alliance. Wi-Fi provides
35 (http://www.wi-fi.org/OpenSection/protected_access.asp).</para>
39 40-bit keys, 24-bit initialization vector (IV), and CRC32 to
44 makes attacks easier, there is no replay protection, and non-keyed
49 uses Temporal Key Integrity Protocol (TKIP) to replace WEP. TKIP
52 per-packet RC4 keys. In addition, it implements replay protection,
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_sve.td1 //===--- arm_sve.td - ARM SVE compiler interface ------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // https://developer.arm.com/architectures/system-architectures/software-standards/acle
14 //===----------------------------------------------------------------------===//
123 // First-faulting load one vector (scalar base)
132 // First-faulting load one vector (scalar base, VL displacement)
148 // First-faulting load one vector (vector base)
157 // First-faulting load one vector (scalar base, signed vector offset in bytes)
172 // First-faulting load one vector (scalar base, unsigned vector offset in bytes)
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA510.td1 //==- AArch64SchedCortexA510.td - ARM Cortex-A510 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for the ARM Cortex-A510 processor.
11 //===----------------------------------------------------------------------===//
13 // ===---------------------------------------------------------------------===//
14 // The following definitions describe the per-operand machine model.
17 // Cortex-A510 machine model for scheduling and other instruction cost heuristics.
19 let MicroOpBufferSize = 0; // The Cortex-A510 is an in-order processor
20 let IssueWidth = 3; // It dual-issues under most circumstances
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H A DAArch64SchedNeoverseN2.td1 //=- AArch64SchedNeoverseN2.td - NeoverseN2 Scheduling Defs --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 let IssueWidth = 10; // Micro-ops dispatched at a time.
15 let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer.
18 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
25 //===----------------------------------------------------------------------===//
27 // Instructions are first fetched and then decoded into internal macro-ops
29 // stages. A MOP can be split into two micro-ops further down the pipeline
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H A DAArch64SchedNeoverseV2.td1 //=- AArch64SchedNeoverseV2.td - NeoverseV2 Scheduling Defs --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p2
14 //===----------------------------------------------------------------------===//
17 let IssueWidth = 16; // Micro-ops dispatched at a time.
18 let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
21 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
29 //===----------------------------------------------------------------------===//
31 // Instructions are first fetched and then decoded into internal macro-ops
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/freebsd/contrib/wpa/hostapd/
H A DREADME1 hostapd - user space IEEE 802.11 AP and IEEE 802.1X/WPA/WPA2/EAP
5 Copyright (c) 2002-2024, Jouni Malinen <j@w1.fi> and contributors
17 -------
33 3. Neither the name(s) of the above-listed copyright holder(s) nor the
68 ------------
71 - drivers:
73 (http://w1.fi/hostap-driver.html)
77 mac80211-based drivers that support AP mode (with driver=nl80211).
84 FreeBSD -current
89 -------------------
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/freebsd/contrib/netbsd-tests/net/ndp/
H A Dt_ra.sh1 # $NetBSD: t_ra.sh,v 1.24 2017/01/13 08:11:01 ozaki-r Exp $
47 DEBUG=${DEBUG:-true}
53 atf_check -s exit:0 -o match:'0.->.1' rump.sysctl -w net.inet6.ip6.forwarding=1
55 atf_check -s exit:0 mkdir -p /rump/var/chroot/rtadvd
68 atf_check -s exit:0 rump.ifconfig shmif0 inet6 ${IP6ADDR}
69 atf_check -s exit:0 rump.ifconfig shmif0 up
70 atf_check -s exit:0 rump.ifconfig -w 10
80 while [ -f ${PIDFILE} ]
103 atf_check -s exit:0 rump.rtadvd -c ${CONFIG} -p $pidfile shmif0
104 while [ ! -f $pidfile ]; do
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/freebsd/lib/libsys/
H A Dopen.2139 MIB is set to zero, ".." is not allowed if found on non-local filesystem.
147 .Bl -tag -width O_RESOLVE_BENEATH
270 link points to a non-existent name.
281 The descriptor remains in non-blocking mode for subsequent operations.
367 The run-time linker (rtld) uses this flag to ensure shared objects have
375 Absolute paths or even the temporal escape from beneath of the starting
404 the following descriptor-level operations:
406 .Bl -tag -width __acl_aclcheck_fd -offset indent -compact
469 returns a non-negative integer, termed a file descriptor.
470 It returns \-1 on failure.
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatternsHVX.td1 //===- HexagonPatternsHVX.td - Selection Patterns for HVX --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
40 const auto &ST = CurDAG->getSubtarget<HexagonSubtarget>();
41 return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32);
44 def Q2V: OutPatFrag<(ops node:$Qs), (V6_vandqrt $Qs, (ToI32 -1))>;
55 (ToI32 -1))>;
95 int32_t V = N->getSExtValue();
96 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
98 if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
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/freebsd/contrib/llvm-project/llvm/tools/llvm-profdata/
H A Dllvm-profdata.cpp1 //===- llvm-profdata.cpp - LLVM profile data tool -------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // llvm-profdata merges .profdata files.
11 //===----------------------------------------------------------------------===//
51 // https://llvm.org/docs/CommandGuide/llvm-profdata.html has documentations
57 "https://llvm.org/docs/CommandGuide/llvm-profdata.html#profdata-show");
60 "Reads temporal profiling traces from a profile and outputs a function "
63 "https://llvm.org/docs/CommandGuide/llvm-profdata.html#profdata-order");
68 "https://llvm.org/docs/CommandGuide/llvm-profdata.html#profdata-overlap");
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/freebsd/sys/contrib/ck/src/
H A Dck_epoch.c2 * Copyright 2011-2015 Samy Al Bahra.
29 * Fraser, K. 2004. Practical Lock-Freedom. PhD Thesis, University
57 * from). This guarantees us that for any given value e_g, any threads with-in
59 * an e value of e_g-1 or e_g. This also means that hazardous references may be
60 * shared in both e_g-1 and e_g even if they are logically deleted in e_g.
65 * executing some hash table look-ups, while some other writer thread (which
68 * This is possible if the writer thread re-observes the epoch after the
71 * Psuedo-code for writer:
79 * Psuedo-code for reader:
82 * ck_pr_inc(&x->value);
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/freebsd/sys/amd64/include/
H A Datomic.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 * Therefore, except for special cases, like non-temporal memory accesses or
63 * The open-coded number is used instead of the symbolic expression to
82 * atomic_subtract_char(P, V) (*(u_char *)(P) -= (V))
87 * atomic_subtract_short(P, V) (*(u_short *)(P) -= (V))
92 * atomic_subtract_int(P, V) (*(u_int *)(P) -= (V))
99 * atomic_subtract_long(P, V) (*(u_long *)(P) -= (V))
146 * Returns 0 on failure, non-zero on success.
289 * special address for "mem". In the kernel, we use a private per-cpu
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineMemOperand.h1 //==- llvm/CodeGen/MachineMemOperand.h - MachineMemOperand class -*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
45 /// Offset - This is an offset from the base Value*.
55 AddrSpace = v ? v->getType()->getPointerAddressSpace() : 0; in V()
61 AddrSpace = v ? v->getAddressSpace() : 0; in V()
75 AddrSpace = ValPtr->getType()->getPointerAddressSpace(); in V()
77 AddrSpace = cast<const PseudoSourceValue *>(V)->getAddressSpace(); in V()
121 //===----------------------------------------------------------------------===//
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