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/linux/arch/x86/math-emu/
H A D	reg_round.S	1 /* SPDX-License-Identifier: GPL-2.0 / 3 /---------------------------------------------------------------------------+ 10 \| Australia. E-mail billm@suburbia.net \| 20 \| Return value is the tag of the answer, or-ed with FPU_Exception if \| 21 \| one was raised, or -1 on internal error. \| 26 +---------------------------------------------------------------------------/ 28 /---------------------------------------------------------------------------+ 47 \| must be non-zero. \| 48 \| If the significand extension is non-zero then the significand is \| 52 \| non-zero values: \| [all …]
H A D	errors.c	1 // SPDX-License-Identifier: GPL-2.0 2 /---------------------------------------------------------------------------+ 5 \| The error handling functions for wm-FPU-emu \| 9 \| E-mail billm@jacobi.maths.monash.edu.au \| 12 +---------------------------------------------------------------------------/ 14 /---------------------------------------------------------------------------+ 19 +---------------------------------------------------------------------------/ 191 printk("st(%d) %c .%04lx %04lx %04lx %04lx e%+-6d ", i, in FPU_printall() 192 getsign(r) ? '-' : '+', in FPU_printall() 193 (long)(r->sigh >> 16), in FPU_printall() [all …]
/linux/Documentation/admin-guide/perf/
H A D	imx-ddr.rst	23 .. code-block:: bash 25 perf stat -a -e imx8_ddr0/cycles/ cmd 26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd 28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) 33 un-supported, and value 1 for supported. 37 --AXI_ID defines AxID matching value. 38 --AXI_MASKING defines which bits of AxID are meaningful for the matching. 40 - 0: corresponding bit is masked. 41 - 1: corresponding bit is not masked, i.e. used to do the matching. 44 When non-masked bits are matching corresponding AXI_ID bits then counter is [all …]
/linux/drivers/xen/events/
H A D	events_2l.c	1 // SPDX-License-Identifier: GPL-2.0 3 * Xen event channels (2-level ABI) 19 #include <xen/xen-ops.h> 65 sync_clear_bit(port, BM(&s->evtchn_pending[0])); in evtchn_2l_clear_pending() 71 sync_set_bit(port, BM(&s->evtchn_pending[0])); in evtchn_2l_set_pending() 77 return sync_test_bit(port, BM(&s->evtchn_pending[0])); in evtchn_2l_is_pending() 83 sync_set_bit(port, BM(&s->evtchn_mask[0])); in evtchn_2l_mask() 107 sync_clear_bit(port, BM(&s->evtchn_mask[0])); in evtchn_2l_unmask() 108 evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0])); in evtchn_2l_unmask() 111 sync_set_bit(port, BM(&s->evtchn_mask[0])); in evtchn_2l_unmask() [all …]
H A D	events_fifo.c	2 * Xen event channels (FIFO-based ABI) 49 #include <xen/xen-ops.h> 112 q->head[i] = 0; in init_control_block() 149 return -EINVAL; in evtchn_fifo_setup() 160 ret = -ENOMEM; in evtchn_fifo_setup() 191 /* no-op / in evtchn_fifo_bind_to_cpu() 215 sync_set_bit(EVTCHN_FIFO_BIT(MASKED, word), BM(word)); in evtchn_fifo_mask() 221 return sync_test_bit(EVTCHN_FIFO_BIT(MASKED, word), BM(word)); in evtchn_fifo_is_masked() 224 Clear MASKED if not PENDING, spinning if BUSY is set. 282 head = q->head[priority]; in consume_one_event() [all …]
/linux/arch/powerpc/kvm/
H A D	book3s_xive.c	1 // SPDX-License-Identifier: GPL-2.0-only 6 #define pr_fmt(fmt) "xive-kvm: " fmt 23 #include <asm/xive-regs.h> 33 #define __x_eoi_page(xd) ((void __iomem )((xd)->eoi_mmio)) 34 #define __x_trig_page(xd) ((void __iomem )((xd)->trig_mmio)) 65 xc->pending \|= 1 << cppr; in xive_vm_ack_pending() 68 if (cppr >= xc->hw_cppr) in xive_vm_ack_pending() 69 pr_warn("KVM-XIVE: CPU %d odd ack CPPR, got %d at %d\n", in xive_vm_ack_pending() 70 smp_processor_id(), cppr, xc->hw_cppr); in xive_vm_ack_pending() 74 * xc->cppr, this will be done as we scan for interrupts in xive_vm_ack_pending() [all …]
H A D	book3s_xics.c	1 // SPDX-License-Identifier: GPL-2.0-only 50 * - To speed up resends, keep a bitmap of "resend" set bits in the 53 * - Speed up server# -> ICP lookup (array ? hash table ?) 55 * - Make ICS lockless as well, or at least a per-interrupt lock or hashed 59 /* -- ICS routines -- / 81 return -EINVAL; in ics_deliver_irq() 83 state = &ics->irq_state[src]; in ics_deliver_irq() 84 if (!state->exists) in ics_deliver_irq() 85 return -EINVAL; in ics_deliver_irq() 96 if (!state->lsi && level == 0) / noop for MSI */ in ics_deliver_irq() [all …]
H A D	book3s_hv_rm_xics.c	1 // SPDX-License-Identifier: GPL-2.0-only 19 #include <asm/ppc-opcode.h> 20 #include <asm/pnv-pci.h> 37 /* -- ICS routines -- / 44 struct ics_irq_state state = &ics->irq_state[i]; in ics_rm_check_resend() 45 if (state->resend) in ics_rm_check_resend() 46 icp_rm_deliver_irq(xics, icp, state->number, true); in ics_rm_check_resend() 51 /* -- ICP routines -- / 59 kvmppc_host_rm_ops_hv->rm_core[hcore].rm_data = vcpu; in icp_send_hcore_msg() 78 Returns -1, if no CPU could be found in the host [all …]
/linux/arch/powerpc/kernel/
H A D	exceptions-64s.S	1 /* SPDX-License-Identifier: GPL-2.0 / 3 This file contains the 64-bit "server" PowerPC variant 18 #include <asm/exception-64s.h> 21 #include <asm/head-64.h> 22 #include <asm/feature-fixups.h> 28 * EXC_REAL_BEGIN/END - real, unrelocated exception vectors 29 * EXC_VIRT_BEGIN/END - virt (AIL), unrelocated exception vectors 30 * TRAMP_REAL_BEGIN - real, unrelocated helpers (virt may call these) 31 * TRAMP_VIRT_BEGIN - virt, unreloc helpers (in practice, real can use) 32 * EXC_COMMON - After switching to virtual, relocated mode. [all …]
/linux/Documentation/filesystems/
H A D	adfs.rst	`1 .. SPDX-License-Identifier: GPL-2.0 4 Acorn Disc Filing System - ADFS 8 ----------------------------- 12 - new maps 13 - new directories or big directories 17 - E and E+, with or without boot block 18 - F and F+ 32 ---------------------- 49 ------------------------------------------------ 53 - Owner read [all …]`
/linux/drivers/gpu/drm/i915/gt/
H A D	intel_rps_types.h	`1 /* SPDX-License-Identifier: MIT / 41 struct intel_rps_freq_caps - rps freq capabilities 42 * @rp0_freq: non-overclocked max frequency 60 * i915->irq_lock 70 /* PM interrupt bits that should never be masked / 92 u8 efficient_freq; / AKA RPe. Pre-determined balanced frequency / 94 u8 rp0_freq; / Non-overclocked max frequency. */`
/linux/Documentation/devicetree/bindings/arm/tegra/
H A D	nvidia,tegra194-cbb.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sumit Gupta <sumitg@nvidia.com> 15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various 20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC" 26 SError or Data Abort is masked and the error is reported with interrupt. 28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the 31 - For other initiators, the ERD is disabled. So, the access issuing [all …]
/linux/Documentation/arch/powerpc/
H A D	cpu_features.rst	8 This document describes the system (including self-modifying code) used in the 10 compile-time selection. 18 arch/powerpc/kernel/cputable.c. The PVR register is masked and compared with 23 C code may test 'cur_cpu_spec[smp_processor_id()]->cpu_features' for a 28 several paths that are performance-critical and would suffer if an array 30 performance penalty but still allow for runtime (rather than compile-time) CPU 32 based on CPU 0's capabilities, so a multi-processor system with non-identical 53 cur_cpu_spec[0]->cpu_features) or is cleared, respectively. These two macros
H A D	dexcr.rst	1 .. SPDX-License-Identifier: GPL-2.0-or-later 11 PowerPC ISA 3.1B (Power10) that allows per-cpu control over several dynamic 13 branch target prediction) and enabling return-oriented programming (ROP) 24 A hypervisor-privileged SPR that can control aspects for the hypervisor and 27 An optional ultravisor-privileged SPR that can control aspects for the ultravisor. 30 provides a non-privileged read-only view of the userspace DEXCR aspects. 31 There is also an SPR that provides a read-only view of the hypervisor enforced 40 ----- 52 .. flat-table:: 53 :header-rows: 1 [all …]
/linux/arch/microblaze/kernel/
H A D	entry.S	2 * Low-level system-call handling, trap handlers and context-switching 4 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 5 * Copyright (C) 2008-2009 PetaLogix 25 #include <asm/asm-offsets.h> 160 /* Define how to call high-level functions. With MMU, virtual mode must be 161 * enabled when calling the high-level function. Clobbers R11. 263 /* Kernel-mode state save. / \ 264 / Reload kernel stack-ptr. / \ 268 / addik r1, r1, -PT_SIZE; */ \ 269 addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - PT_SIZE; \ [all …]
/linux/drivers/misc/lkdtm/
H A D	stackleak.c	1 // SPDX-License-Identifier: GPL-2.0 20 * masked and instrumentation of this function is disabled. We assume that the 21 * compiler will create a fixed-size stack frame for this function. 23 * Any non-inlined function may make further use of the stack, altering the 34 const unsigned long lowest_sp = current->lowest_stack; in check_stackleak_irqoff() 48 current_sp, task_stack_low, task_stack_high - 1); in check_stackleak_irqoff() 54 pr_err("FAIL: current->lowest_stack (0x%lx) outside of task stack bounds [0x%lx..0x%lx]\n", in check_stackleak_irqoff() 55 lowest_sp, task_stack_low, task_stack_high - 1); in check_stackleak_irqoff() 65 * Poison values are naturally-aligned unsigned longs. As the current in check_stackleak_irqoff() 86 poison_low -= sizeof(unsigned long); in check_stackleak_irqoff() [all …]
/linux/arch/powerpc/include/asm/nohash/32/
H A D	pte-8xx.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 21 These will get masked from the level 2 descriptor at TLB load time, and 38 /* These 4 software bits must be masked out when the L2 entry is loaded 56 /* cache related flags non existing on 8xx */ 84 #include <asm/pgtable-masks.h> 138 pte_update(vma->vm_mm, address, ptep, clr, set, huge); in __ptep_set_access_flags() 231 pte_basic_t val = READ_ONCE(ptep->pte); in ptep_get()`
/linux/net/openvswitch/
H A D	actions.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2007-2017 Nicira, Inc. 69 #define OVS_DEFERRED_ACTION_THRESHOLD (OVS_RECURSION_LIMIT - 2) 85 /* Make a clone of the 'key', using the pre-allocated percpu 'flow_keys' 95 key = &keys->key[level - 1]; in clone_key() 104 fifo->head = 0; in action_fifo_init() 105 fifo->tail = 0; in action_fifo_init() 110 return (fifo->head == fifo->tail); in action_fifo_is_empty() 118 return &fifo->fifo[fifo->tail++]; in action_fifo_get() 123 if (fifo->head >= DEFERRED_ACTION_FIFO_SIZE - 1) in action_fifo_put() [all …]
H A D	flow_netlink.c	`1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2007-2017 Nicira, Inc. 49 #define OVS_ATTR_NESTED -1 50 #define OVS_ATTR_VARIABLE -2 103 range = &match->range; in update_range() 105 range = &match->mask->range; in update_range() 107 if (range->start == range->end) { in update_range() 108 range->start = start; in update_range() 109 range->end = end; in update_range() 113 if (range->start > start) in update_range() [all …]`
/linux/arch/mips/dec/
H A D	int-handler.S	`1 /* SPDX-License-Identifier: GPL-2.0 / 12 Rewritten extensively for controller-driven IRQ support 51 * off, nothing in between like BSD spl() brain-damage. 59 * -------- ------ 72 * -------- ------ 85 * -------- ------ 98 * -------- ------ 105 * 6 Halt Keycode from Access.Bus keyboard (CTRL-ALT-ENTER) 111 * -------- ------ 137 andi t0,ST0_IM # CAUSE.CE may be non-zero! [all …]`
/linux/Documentation/filesystems/spufs/
H A D	spu_run.rst	1 .. SPDX-License-Identifier: GPL-2.0 10 spu_run - execute an spu context 25 Cell Broadband Engine Architecture in order to access Synergistic Pro- 26 cessor Units (SPUs). It uses the fd that was returned from spu_cre- 27 ate(2) to address a specific SPU context. When the context gets sched- 32 not return while the SPU is still running. If there is a need to exe- 42 gets filled when spu_run returns. It can be one of the following con- 59 spu_run returns the value of the spu_status register or -1 to indicate 62 optionally a 14 bit code returned from the stop-and-signal instruction 66 SPU was stopped by stop-and-signal. [all …]
/linux/Documentation/trace/coresight/
H A D	coresight-etm4x-reference.rst	`11 --------------------------- 20 ---- 37 ---- 47 ---- 52 - > 0 : Programs up the hardware with the current values held in the driver 55 - = 0 : disable trace hardware. 60 ---- 72 ---- 77 When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for trace session. Otherwise -1 86 ---- [all …]`
/linux/kernel/irq/
H A D	pm.c	1 // SPDX-License-Identifier: GPL-2.0 18 if (irqd_is_wakeup_armed(&desc->irq_data)) { in irq_pm_check_wakeup() 19 irqd_clear(&desc->irq_data, IRQD_WAKEUP_ARMED); in irq_pm_check_wakeup() 20 desc->istate \|= IRQS_SUSPENDED \| IRQS_PENDING; in irq_pm_check_wakeup() 21 desc->depth++; in irq_pm_check_wakeup() 30 * Called from __setup_irq() with desc->lock held after @action has 35 desc->nr_actions++; in irq_pm_install_action() 37 if (action->flags & IRQF_FORCE_RESUME) in irq_pm_install_action() 38 desc->force_resume_depth++; in irq_pm_install_action() 40 WARN_ON_ONCE(desc->force_resume_depth && in irq_pm_install_action() [all …]
/linux/drivers/gpu/drm/xe/
H A D	xe_mmio.c	`1 // SPDX-License-Identifier: MIT 3 * Copyright © 2021-2023 Intel Corporation 9 #include <linux/io-64-nonatomic-lo-hi.h> 33 tile->mmio.regs = NULL; in tiles_fini() 37 * On multi-tile devices, partition the BAR space for MMIO on each tile, 43 * .----------------------. <- tile_count * tile_mmio_size 45 * \|----------------------\| <- 2 * tile_mmio_size 47 * \|----------------------\| <- 1 * tile_mmio_size + 4MB 48 * \| tile1->mmio.regs \| 49 * \|----------------------\| <- 1 * tile_mmio_size [all …]`
/linux/Documentation/hwmon/
H A D	adm1026.rst	16 - Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing 17 - Justin Thiessen <jthiessen@penguincomputing.com> 20 ----------------- 23 List of GPIO pins (0-16) to program as inputs 26 List of GPIO pins (0-16) to program as outputs 29 List of GPIO pins (0-16) to program as inverted 32 List of GPIO pins (0-16) to program as normal/non-inverted 35 List of GPIO pins (0-7) to program as fan tachs 39 ----------- 45 16 general purpose digital I/O lines, eight (8) fan speed sensors (8-bit), [all …]

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