| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | uncore-interconnect.json | 12 …n till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.…
21 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
31 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in Dir…
36 …"PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in Dire…
41 … "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
50 … "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
55 … "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
60 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and…
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| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | uncore-interconnect.json | 3 …. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access…
8 …. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access…
22 …n till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.…
31 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
41 … "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
50 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and…
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| /linux/arch/riscv/mm/ |
| H A D | dma-noncoherent.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V specific functions to support DMA for non-coherent devices
8 #include <linux/dma-direct.h>
9 #include <linux/dma-map-ops.h>
12 #include <asm/dma-noncoherent.h>
131 void arch_setup_dma_ops(struct device *dev, bool coherent) in arch_setup_dma_ops() argument
133 WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN, in arch_setup_dma_ops()
135 "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)", in arch_setup_dma_ops()
139 WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC, in arch_setup_dma_ops()
140 "%s %s: device non-coherent but no non-coherent operations supported", in arch_setup_dma_ops()
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | uncore-interconnect.json | 21 …ing for data returning from the memory controller. Accounts for coherent and non-coherent requests…
30 …are waiting for data return from memory controller. Account for coherent and non-coherent requests…
40 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
50 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
77 "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
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| /linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | uncore-interconnect.json | 21 …ing for data returning from the memory controller. Accounts for coherent and non-coherent requests…
30 …are waiting for data return from memory controller. Account for coherent and non-coherent requests…
40 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
50 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
77 "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
|
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | uncore-interconnect.json | 12 …"BriefDescription": "Each cycle counts number of any coherent requests at memory controller that w…
22 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
32 …"BriefDescription": "Each cycle counts number of valid coherent Data Read entries. Such entry is d…
42 "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches",
52 … from its allocation in ReqTrk until deallocation. Accounts for Coherent and non-coherent traffic.…
62 …"BriefDescription": "Each cycle counts number of valid coherent Data Read entries. Such entry is d…
72 …: "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
81 …"BriefDescription": "Counts number of all coherent Data Read entries. Does not include prefetches.…
|
| /linux/arch/mips/kernel/ |
| H A D | pm-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <asm/asm-offsets.h>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
22 #include <asm/smp-cps.h>
26 * cps_nc_entry_fn - type of a generated non-coherent state entry function
28 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
30 * The code entering & exiting non-coherent states is generated at runtime
33 * core-specific code particularly for cache routines. If coupled_coherence
34 * is non-zero and this is the entry function for the CPS_PM_NC_WAIT state,
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | uncore-interconnect.json | 12 …ts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.…
21 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
49 …"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose da…
58 …"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose da…
67 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and…
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| /linux/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_object_types.h | 2 * SPDX-License-Identifier: MIT
64 * shrink - Perform further backend specific actions to facilate
71 * I915_GEM_OBJECT_SHRINK_WRITEBACK - Try to perform writeback of the
74 * I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT - Don't wait for the object to
94 * adjust_lru - notify that the madvise value was updated
103 * delayed_free - Override the default delayed free implementation
108 * migrate - Migrate object to a different region either for
122 * enum i915_cache_level - The supported GTT caching values for system memory
127 * coherent with the GPU, when also reading or writing through the CPU cache
136 * GPU access is not coherent with the CPU cache. If the cache is dirty
[all …]
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| /linux/arch/riscv/ |
| H A D | Kconfig.errata | 20 non-standard handling on non-coherent operations on Andes cores.
35 bool "Apply SiFive errata CIP-453"
39 This will apply the SiFive CIP-453 errata to add sign extension
46 bool "Apply SiFive errata CIP-1200"
50 This will apply the SiFive CIP-1200 errata to repalce all
68 caches that are non-coherent with respect to peripheral DMAs.
69 It was designed before the Zicbom extension so needs non-standard
76 bool "T-HEAD errata"
79 All T-HEAD errata Kconfig depend on this Kconfig. Disabling
80 this Kconfig will disable all T-HEAD errata. Please say "Y"
[all …]
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| /linux/arch/arc/mm/ |
| H A D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 #include <linux/dma-map-ops.h>
12 * - hardware IOC not available (or "dma-coherent" not set for device in DT)
13 * - But still handle both coherent and non-coherent requests from caller
15 * For DMA coherent hardware (IOC) generic code suffices
23 * Yeah this bit us - STAR 9000898266 in arch_dma_prep_coherent()
37 * dma-mapping: provide a generic dma-noncoherent implementation)"
40 * |----------------------------------------------------------------
48 * upper layer functions (in include/linux/dma-mapping.h)
[all …]
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| /linux/drivers/cpuidle/ |
| H A D | cpuidle-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <asm/pm-cps.h>
16 STATE_WAIT = 0, /* MIPS wait instruction, coherent */
17 STATE_NC_WAIT, /* MIPS wait instruction, non-coherent */
36 if (cpus_are_siblings(0, dev->cpu) && (index > STATE_NC_WAIT)) in cps_nc_enter()
52 return -EINVAL; in cps_nc_enter()
57 return -EINTR; in cps_nc_enter()
78 .name = "nc-wait",
79 .desc = "non-coherent MIPS wait",
86 .name = "clock-gated",
[all …]
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | vidioc-reqbufs.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_REQBUFS - Initiate Memory Mapping, User Pointer I/O or DMA buffer I/O
78 .. flat-table:: struct v4l2_requestbuffers
79 :header-rows: 0
80 :stub-columns: 0
83 * - __u32
84 - ``count``
85 - The number of buffers requested or granted.
86 * - __u32
87 - ``type``
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | uncore-interconnect.json | 12 …"BriefDescription": "Each cycle counts number of any coherent request at memory controller that we…
22 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
54 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
64 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
74 …d from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.…
83 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
93 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
102 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
|
| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | uncore-interconnect.json | 12 …"BriefDescription": "Each cycle counts number of any coherent request at memory controller that we…
22 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
54 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
64 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
74 …d from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.…
83 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
93 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
102 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
|
| /linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | uncore-io.json | 17 …These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages…
27 …These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages…
37 …These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages…
47 …the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages…
57 …the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages…
67 …the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages…
77 …These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages…
87 …These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages…
97 …These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages…
|
| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | uncore-interconnect.json | 12 …"BriefDescription": "Each cycle counts number of any coherent request at memory controller that we…
22 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
54 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
64 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
74 … from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.…
83 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
102 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
|
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | uncore-interconnect.json | 3 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
22 "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches",
58 …: "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
|
| /linux/Documentation/filesystems/ |
| H A D | sysv-fs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 - Xenix FS,
9 - SystemV/386 FS,
10 - Coherent FS.
14 * Answer the 'System V and Coherent filesystem support' question with 'y'
18 mount [-r] -t sysv device mountpoint
22 -t sysv
23 -t xenix
24 -t coherent
30 - Coherent FS:
[all …]
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| /linux/arch/mips/mm/ |
| H A D | dma-noncoherent.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2000, 2001, 06 Ralf Baechle <ralf@linux-mips.org>
7 #include <linux/dma-direct.h>
8 #include <linux/dma-map-ops.h>
12 #include <asm/cpu-type.h>
18 * flush post-DMA.
20 * Warning on the terminology - Linux calls an uncached area coherent; MIPS
21 * terminology calls memory areas with hardware maintained coherency coherent.
24 * However this function is only called on non-I/O-coherent systems and only the
41 * the post-DMA flush/invalidate. in cpu_needs_post_dma_flush()
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | uncore-interconnect.json | 45 "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches",
77 …: "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
|
| /linux/Documentation/arch/xtensa/ |
| H A D | atomctl.rst | 9 1. With and without an Coherent Cache Controller which
22 doing a Cached (WB) transaction and use the Memory RCW for un-cached
25 For systems without an coherent cache controller, non-MX, we always
26 use the memory controllers RCW, though non-MX controllers likely
29 CUSTOMER-WARNING:
45 Values WB - Write Back WT - Write Thru BY - Bypass
|
| /linux/drivers/ras/amd/atl/ |
| H A D | internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
27 /* Maximum possible number of Coherent Stations within a single Data Fabric. */
110 * divisible by 5. Power-of-two interleave modes are handled
147 * These masks operate on the 16-bit Coherent Station IDs,
156 * Least-significant bit of Node ID portion of the
157 * system-wide Coherent Station Fabric ID.
162 * Least-significant bit of Die portion of the Node ID.
164 * to the Coherent Station Fabric ID.
169 * Least-significant bit of Socket portion of the Node ID.
171 * to the Coherent Station Fabric ID.
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | uncore-interconnect.json | 3 … "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
9 …"PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. …
31 "BriefDescription": "FAF - request insert from TC.",
47 "BriefDescription": "FAF allocation -- sent to ADQ",
84 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
94 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
104 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
114 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
124 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
134 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | uncore-interconnect.json | 3 … "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
9 …"PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. …
31 "BriefDescription": "FAF - request insert from TC.",
47 "BriefDescription": "FAF allocation -- sent to ADQ",
84 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
94 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
104 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
114 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
124 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
134 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
[all …]
|