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/linux/arch/arm/boot/dts/hisilicon/
H A Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-catu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Coresight Address Translation Unit (CATU)
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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/linux/Documentation/trace/coresight/
H A Dcoresight-cpu-debug.rst2 Coresight CPU Debug Module
9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
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H A Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
4 CoreSight Embedded Cross Trigger (CTI & CTM).
11 --------------------
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
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H A Dcoresight-etm4x-reference.rst11 ---------------------------
13 Root: ``/sys/bus/coresight/devices/etm<N>``
20 ----
37 ----
47 ----
52 - > 0 : Programs up the hardware with the current values held in the driver
55 - = 0 : disable trace hardware.
60 ----
72 ----
77 When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for trace session. Otherwise -1
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-platform.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/coresight.h>
19 #include "coresight-priv.h"
24 * If the output port is already assigned on this device, return -EINVAL
37 for (i = 0; i < pdata->nr_outconns; ++i) { in coresight_add_out_conn()
38 conn = pdata->out_conns[i]; in coresight_add_out_conn()
39 /* Output == -1 means ignore the port for example for helpers */ in coresight_add_out_conn()
40 if (conn->src_port != -1 && in coresight_add_out_conn()
41 conn->src_port == new_conn->src_port) { in coresight_add_out_conn()
43 conn->src_port); in coresight_add_out_conn()
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H A Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/coresight.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
23 #define CTI_DT_CONNS "trig-conns"
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
27 #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc"
28 #define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs"
29 #define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs"
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H A Dcoresight-cti-core.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/coresight.h>
22 #include "coresight-priv.h"
23 #include "coresight-cti.h"
26 * CTI devices can be associated with a PE, or be connected to CoreSight
30 * We assume that the non-CPU CTIs are always powered as we do with sinks etc.
43 dev_get_drvdata(csdev->dev.parent)
56 * CTI device name list - for CTI not bound to cores.
60 /* write set of regs to hardware - call with spinlock claimed */
63 struct cti_config *config = &drvdata->config; in cti_write_all_hw_regs()
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/linux/tools/perf/util/
H A Dcs-etm.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 /* PMU->type (32 bit), total # of CPUs (32 bit) */
40 * CoreSight Trace ID. ...TRACEIDR metadata will be set to legacy values
65 /* define fixed version 0 length - allow new format reader to read old files. */
66 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1)
83 /* define fixed version 0 length - allow new format reader to read old files. */
84 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1)
106 * Check for valid CoreSight trace ID. If an invalid value is present in the metadata,
114 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
136 * table 6-12 Possible values for the TYPE field in an Exception instruction
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H A Dcs-etm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(C) 2015-2018 Linaro Limited.
12 #include <linux/coresight-pmu.h>
22 #include "cs-etm.h"
23 #include "cs-etm-decoder/cs-et
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/linux/arch/arm64/boot/dts/sprd/
H A Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
51 compatible = "arm,cortex-a55";
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/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
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/linux/tools/perf/
H A DMakefile.perf1 # SPDX-License-Identifier: GPL-2.0-only
16 # Define ARCH as name of target architecture if you want cross-builds.
18 # Define CROSS_COMPILE as prefix name of compiler if you want cross-builds.
27 # Define PYTHON_CONFIG to point to the python-config binary if
28 # the default `$(PYTHON)-config' is not correct.
34 # Define LDFLAGS=-static to build a static binary.
36 # Define EXTRA_CFLAGS=-m64 or EXTRA_CFLAGS=-m32 as appropriate for cross-builds.
38 # Define EXCLUDE_EXTLIBS=-lmylib to exclude libmylib from the auto-generated
43 # Define NO_LIBDW if you do not want debug-info analysis feature at all.
53 # Define NO_LIBELF if you do not want libelf dependency (e.g. cross-builds)
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H A Dcheck-headers.sh2 # SPDX-License-Identifier: GPL-2.0
7 declare -a FILES=(
34 "include/linux/list-sort.h"
39 "arch/x86/include/asm/msr-index.h"
40 "arch/x86/lib/x86-opcode-map.txt"
41 "arch/x86/tools/gen-insn-attr-x86.awk"
65 "include/asm-generic/bitops/arch_hweight.h"
66 "include/asm-generic/bitops/const_hweight.h"
67 "include/asm-generic/bitops/__fls.h"
68 "include/asm-generic/bitops/fls.h"
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H A DMakefile.config1 # SPDX-License-Identifier: GPL-2.0-only
3 ifeq ($(src-perf),)
4 src-perf := $(srctree)/tools/perf
7 ifeq ($(obj-perf),)
8 obj-perf := $(OUTPUT)
11 ifneq ($(obj-perf),)
12 obj-perf := $(abspath $(obj-perf))/
15 $(shell printf "" > $(OUTPUT).config-detected)
16 detected = $(shell echo "$(1)=y" >> $(OUTPUT).config-detected)
17 detected_var = $(shell echo "$(1)=$($(1))" >> $(OUTPUT).config-detected)
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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H A Dimx7d.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
18 clock-frequency = <996000000>;
19 operating-points-v2 = <&cpu0_opp_table>;
20 #cooling-cells = <2>;
21 nvmem-cells = <&fuse_grade>;
22 nvmem-cell-names = "speed_grade";
26 compatible = "arm,cortex-a7";
29 clock-frequency = <996000000>;
30 operating-points-v2 = <&cpu0_opp_table>;
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
11 #include <dt-bindings/gpio/gpio.h>
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/linux/tools/perf/Documentation/
H A Dperf-list.txt1 perf-list(1)
5 ----
6 perf-list - List all symbolic event types
9 --------
15 -----------
17 various perf commands with the -e option.
20 -------
21 -d::
22 --desc::
25 --no-desc::
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H A Dperf-record.txt1 perf-record(1)
5 ----
6 perf-record - Run a command and record its profile into perf.data
9 --------
11 'perf record' [-e <EVENT> | --event=EVENT] [-a] <command>
12 'perf record' [-e <EVENT> | --event=EVENT] [-a] \-- <command> [<options>]
15 -----------
17 from it, into perf.data - without displaying anything.
23 -------
27 -e::
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/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
205 if (hdev->pldm) in goya_coresight_timeout()
219 dev_err(hdev->dev, in goya_coresight_timeout()
220 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in goya_coresight_timeout()
222 return -EFAULT; in goya_coresight_timeout()
236 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in goya_config_stm()
237 dev_err(hdev->dev, "Invalid register index in STM\n"); in goya_config_stm()
238 return -EINVAL; in goya_config_stm()
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in goya_config_stm()
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/clock/nxp,imx95-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx95-clock.h"
14 #include "imx95-pinfunc.h"
15 #include "imx95-power.h"
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/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2018 HabanaLabs, Ltd.
381 dev_err(hdev->dev, in gaudi_coresight_timeout()
382 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in gaudi_coresight_timeout()
384 return -EFAULT; in gaudi_coresight_timeout()
398 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in gaudi_config_stm()
399 dev_err(hdev->dev, "Invalid register index in STM\n"); in gaudi_config_stm()
400 return -EINVAL; in gaudi_config_stm()
403 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in gaudi_config_stm()
407 if (params->enable) { in gaudi_config_stm()
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/linux/tools/include/uapi/linux/
H A Dperf_event.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
13 * For licencing details see kernel-base/COPYING
23 * User-space ABI bits:
37 PERF_TYPE_MAX, /* non-ABI */
78 PERF_COUNT_HW_MAX, /* non-ABI */
84 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
97 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
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