/freebsd/sys/contrib/device-tree/Bindings/arm/ |
H A D | coresight.txt | 1 * CoreSight Components: 3 CoreSight components are compliant with the ARM CoreSight architecture 8 sink. Each CoreSight component device should use these properties to describe 11 * Required properties for all components *except* non-configurable replicators 12 and non-configurable funnels: 16 - Embedded Trace Buffer (version 1.0): 17 "arm,coresight-etb10", "arm,primecell"; 19 - Trace Port Interface Unit: 20 "arm,coresight-tpiu", "arm,primecell"; 22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB), [all …]
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H A D | coresight-cti.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 4 --- 5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: ARM Coresight Cross Trigger Interface (CTI) device. 11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected 12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in 15 not part of the CoreSight graph described in the general CoreSight bindings 16 file coresight.txt. 38 indicate this feature (arm,coresight-cti-v8-arch). [all …]
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H A D | arm,coresight-cti.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 4 --- 5 $id: http://devicetree.org/schemas/arm/arm,coresight [all...] |
H A D | arm,coresight-static-funnel.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Arm CoreSight Static Trace Bus Funnel 10 - Mathieu Poirier <mathieu.poirier@linaro.org> 11 - Mike Leach <mike.leach@linaro.org> 12 - Leo Yan <leo.yan@linaro.org> 13 - Suzuki K Poulose <suzuki.poulose@arm.com> 16 CoreSight components are compliant with the ARM CoreSight architecture [all …]
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H A D | arm,coresight-static-replicator.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Arm CoreSight Static Trace Bus Replicator 10 - Mathieu Poirier <mathieu.poirier@linaro.org> 11 - Mike Leach <mike.leach@linaro.org> 12 - Leo Yan <leo.yan@linaro.org> 13 - Suzuki K Poulose <suzuki.poulose@arm.com> 16 CoreSight components are compliant with the ARM CoreSight architecture [all …]
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H A D | arm,coresight-catu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Arm Coresight Address Translation Unit (CATU) 10 - Mathieu Poirier <mathieu.poirier@linaro.org> 11 - Mike Leach <mike.leach@linaro.org> 12 - Leo Yan <leo.yan@linaro.org> 13 - Suzuki K Poulose <suzuki.poulose@arm.com> 16 CoreSight components are compliant with the ARM CoreSight architecture [all …]
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/freebsd/sys/contrib/device-tree/src/arm/hisilicon/ |
H A D | hip04.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013-2014 HiSilicon Ltd. 6 * Copyright (C) 2013-2014 Linaro Ltd. 12 /* memory bus is 64-bit */ 13 #address-cells = <2>; 14 #size-cells = <2>; 21 compatible = "hisilicon,hip04-bootwrapper"; 22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; 26 #address-cells = <1>; 27 #size-cells = <0>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/sprd/ |
H A D | sc9863a.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <dt-bindings/clock/sprd,sc9863a-clk.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #address-cells = <2>; 15 #size-cells = <0>; 17 cpu-map { 48 compatible = "arm,cortex-a55"; 50 enable-method = "psci"; 51 cpu-idle-states = <&CORE_PD>; 56 compatible = "arm,cortex-a55"; [all …]
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H A D | ums512.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 #include <dt-bindings/clock/sprd,ums512-clk.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 interrupt-parent = <&gic>; 13 #address-cell [all...] |
/freebsd/sys/arm64/coresight/ |
H A D | coresight_etm4x.c | 1 /*- 2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com> 7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing 40 #include <arm64/coresight/coresight.h> 41 #include <arm64/coresight/coresight_etm4x.h> 57 * CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM 58 * CPU1 -> ETM1 -> funnel1 -^ 59 * CPU2 -> ETM2 -> funnel1 -^ 60 * CPU3 -> ETM3 -> funnel1 -^ 65 { -1, 0 } [all …]
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/freebsd/sys/contrib/device-tree/src/arm/arm/ |
H A D | vexpress-v2p-ca15_a7.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 * Cortex-A15_A7 MPCore (V2P-CA15_A7) 8 * HBI-0249A 11 /dts-v1/; 12 #include "vexpress-v2m-rs1.dtsi" 15 model = "V2P-CA15_CA7"; 18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
H A D | sm6115.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 6 #include <dt-bindings/clock/qcom,gcc-sm6115.h> 7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8 #include <dt-binding [all...] |
H A D | msm8916.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 6 #include <dt-bindings/arm/coresight-cti-dt.h> 7 #include <dt-binding [all...] |
H A D | sm8150.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 7 #include <dt-bindings/dma/qcom-gpi.h> 8 #include <dt-bindings/firmware/qcom,scm.h> 9 #include <dt-bindings/interrupt-controlle [all...] |
H A D | sm8250.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8 #include <dt-binding [all...] |
H A D | sc7180.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 10 #include <dt-binding [all...] |
H A D | msm8996.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/qcom,gcc-msm899 [all...] |
H A D | sdm845.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h> 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 11 #include <dt-binding [all...] |
/freebsd/contrib/opencsd/decoder/include/opencsd/ |
H A D | ocsd_if_types.h | 41 /** VS2010 does not support inttypes - remove when VS2010 support is dropped */ 64 typedef uint64_t ocsd_trc_index_t; /**< Trace source index type - 64 bit size */ 67 typedef uint32_t ocsd_trc_index_t; /**< Trace source index type - 32 bit size */ 72 #define OCSD_BAD_TRC_INDEX ((ocsd_trc_index_t)-1) 74 #define OCSD_BAD_CS_SRC_ID ((uint8_t)-1) 92 OCSD_ERR_INVALID_ID, /**< Invalid CoreSight Trace Source ID. */ 99 OCSD_ERR_ATTACH_TOO_MANY, /**< Cannot attach - attach device limit reached. */ 100 OCSD_ERR_ATTACH_INVALID_PARAM, /**< Cannot attach - invalid parameter. */ 101 OCSD_ERR_ATTACH_COMP_NOT_FOUND,/**< Cannot detach - component not found. */ 103 OCSD_ERR_RDR_FILE_NOT_FOUND, /**< source reader - file not found. */ [all …]
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/freebsd/sys/contrib/device-tree/src/arm/qcom/ |
H A D | qcom-apq8064.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/clock/qcom,gcc-msm8960.h> 5 #include <dt-bindings/clock/qcom,lcc-msm8960.h> 6 #include <dt-bindings/reset/qcom,gcc-msm896 [all...] |
H A D | qcom-msm8974.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/interconnect/qcom,msm8974.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/clock/qcom,gcc-msm897 [all...] |
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx7s.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 6 #include <dt-bindings/clock/imx7d-clock.h> 7 #include <dt-bindings/power/imx7-power.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-binding [all...] |
H A D | imx7d.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 7 #include <dt-bindings/reset/imx7-reset.h> 18 clock-frequency = <996000000>; 19 operating-points-v2 = <&cpu0_opp_table>; 20 #cooling-cells = <2>; 21 nvmem-cell [all...] |
/freebsd/sys/contrib/alpine-hal/ |
H A D | al_hal_nb_regs.h | 1 /*- 10 found at http://www.gnu.org/licenses/gpl-2.0.html 101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */ 103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */ 105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */ 107 /* [0x78] Read-only that reflects IOGIC base low address */ 480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity 485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity 512 By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other… 513 …t by primary CPU as part of the initialization process will initiate power-on-reset to this specif… [all …]
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/freebsd/contrib/opencsd/decoder/include/opencsd/etmv4/ |
H A D | trc_pkt_decode_etmv4i.h | 71 …to trace elements. return true to indicate decode complete - can change FSM to commit state - retu… 72 …ancel trace elements generated from latest / prior packets & send to output - may get wait respons… 73 …ocsd_err_t commitElements(); // commit elements - process element stack to generate output packets. 85 // process an exception element - output instruction trace + exception generic type. 109 // sequencing error on packet processing - optionally continue 153 return (m_config->MajVersion() >= ETE_ARCH_VERSION); in isETEConfig() 176 int m_max_spec_depth; // nax depth - from ID reg, beyond which auto-commit occurs 185 // conditional non-branch trace - when data trace active (unsupported at present in the decoder) 191 uint8_t m_CSID; //!< Coresight trace ID for this decoder. 199 NO_SYNC, //!< pre start trace - init state or after reset or overflow, loss of sync. [all …]
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