/linux/Documentation/devicetree/bindings/timer/ |
H A D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marc Zyngier <marc.zyngier@arm.com> 11 - Mark Rutland <mark.rutland@arm.com> 13 ARM cores may have a per-core architected timer, which provides per-cpu timers, 17 The per-core architected timer is attached to a GIC to deliver its 18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC 24 - items: 25 - const: arm,cortex-a15-timer [all …]
|
/linux/arch/arm/mm/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 17 A 32-bit RISC microprocessor based on the ARM7 processor core 36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 53 A 32-bit RISC processor with 8KB cache or 4KB variants, 69 A 32-bit RISC microprocessor based on the ARM9 processor core 182 ARM940T is a member of the ARM9TDMI family of general- 184 instruction and 4KB data cases, each with a 4-word line 190 # ARM946E-S 201 ARM946E-S is a member of the ARM9E-S family of high- 202 performance, 32-bit system-on-chip processor solutions. [all …]
|
H A D | proc-v7.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * linux/arch/arm/mm/proc-v7.S 7 * This is the "shell" of the ARMv7 processor support. 9 #include <linux/arm-smccc.h> 15 #include <asm/asm-offsets.h> 17 #include <asm/pgtable-hwdef.h> 20 #include "proc-macros.S" 23 #include "proc-v7-3level.S" 25 #include "proc-v7-2level.S" 28 .arch armv7-a [all …]
|
H A D | pmsa-v7.c | 52 /* Data-side / unified region attributes */ 76 /* Optional instruction-side region attributes */ 78 /* I-side Region access control register */ 84 /* I-side Region size register */ 90 /* I-side Region base address register */ 108 /* Data-side / unified region attributes */ 137 /* ARMv7-M only supports a unified MPU, so I-side operations are nop */ 149 phys_addr_t abase = base & ~(size - 1); in try_split_region() 150 phys_addr_t asize = base + size - abase; in try_split_region() 157 bdiff = base - abase; in try_split_region() [all …]
|
H A D | alignment.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * Modifications for ARM processor (c) 1995-2001 Russell King 8 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation. 32 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998 52 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */ 72 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */ 107 * CPUs since we spin re-faulting the instruction without in safe_usermode() 158 return -EFAULT; in alignment_proc_write() 160 ai_usermode = safe_usermode(mode - '0', true); in alignment_proc_write() 330 offset.un = -offset.un; in do_alignment_finish_ldst() [all …]
|
/linux/Documentation/trace/coresight/ |
H A D | coresight-cpu-debug.rst | 9 ------------ 11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual 13 debug module and it is mainly used for two modes: self-hosted debug and 16 explore debugging method which rely on self-hosted debug mode, this document 19 The debug module provides sample-based profiling extension, which can be used 21 every CPU has one dedicated debug module to be connected. Based on self-hosted 29 -------------- 31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID 32 registers to decide if sample-based profiling is implemented or not. On some 36 - At the time this documentation was written, the debug driver mainly relies on [all …]
|
/linux/arch/arm/include/asm/ |
H A D | cacheflush.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * Copyright (C) 1999-2002 Russell King 12 #include <asm/glue-cache.h> 17 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) 29 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files 35 * See Documentation/core-api/cachetlb.rst for more information. 37 * effects are cache-type (VIVT/VIPT/PIPT) specific. 42 * Currently only needed for cache-v6.S and cache-v7.S, see 52 * inner shareable and invalidate the I-cache. 65 * - start - user start address (inclusive, page aligned) [all …]
|
H A D | bitops.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 123 #include <asm-generic/bitops/non-atomic.h> 126 * A note about Endian-ness. 127 * ------------------------- 132 * ------------ physical data bus bits ----------- 137 * This means that reading a 32-bit word at address 0 returns the same 147 * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0. 151 * Native endian assembly bitops. nr = 0 -> word 0 bit 0. 161 * Little endian assembly bitops. nr = 0 -> byte 0 bit 0. 170 * Big endian assembly bitops. nr = 0 -> byte 3 bit 0. [all …]
|
/linux/Documentation/arch/arm/ |
H A D | marvell.rst | 13 ------------ 16 - 88F5082 17 - 88F5181 a.k.a Orion-1 18 - 88F5181L a.k.a Orion-VoIP 19 - 88F5182 a.k.a Orion-NAS 21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M… 22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~… 23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800… 24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8… 25 - 88F5281 a.k.a Orion-2 [all …]
|
H A D | kernel_mode_neon.rst | 6 ------------- 10 '-march=armv7-a -mfpu=neon -mfloat-abi=softfp' 18 ------------ 25 non-preemptible section for reasons outlined below. 29 ------------------------- 50 ---------------------------- 67 -------------------- 69 like IEEE-754 compliant underflow handling etc. When the VFP unit needs such 80 --------------------------------------- 84 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the [all …]
|
/linux/arch/arm/common/ |
H A D | secure_cntvoff.S | 1 /* SPDX-License-Identifier: GPL-2.0 */ 13 .arch armv7-a 15 * CNTVOFF has to be initialized either from non-secure Hypervisor 23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
|
H A D | mcpm_head.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * arch/arm/common/mcpm_head.S -- kernel entry point for multi-cluster PM 6 * Copyright: (C) 2012-2013 Linaro Limited 8 * Refer to Documentation/arch/arm/cluster-pm-race-avoidance.rst 18 .arch armv7-a 128 @ Wait for any previously-pending cluster teardown operations to abort 168 @ In the contended case, non-first men wait here for cluster setup 178 @ If a platform-specific CPU setup hook is needed, it is 205 3: .word mcpm_entry_early_pokes - . 206 .word mcpm_entry_vectors - 3b [all …]
|
/linux/arch/arm/ |
H A D | Makefile | 5 # architecture-specific flags and dependencies. 11 # Copyright (C) 1995-2001 by Russell King 13 LDFLAGS_vmlinux := --no-undefined -X --pic-veneer -z norelro 15 LDFLAGS_vmlinux += --be8 16 KBUILD_LDFLAGS_MODULE += --be8 19 GZFLAGS :=-9 20 #KBUILD_CFLAGS +=-pipe 23 KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) 26 KBUILD_CFLAGS += $(call cc-option,-mno-fdpic) 33 MMUEXT := -nommu [all …]
|
/linux/arch/arm64/kernel/ |
H A D | compat_alignment.c | 1 // SPDX-License-Identifier: GPL-2.0-only 16 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998 29 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */ 39 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */ 58 offset.un = -offset.un; in do_alignment_finish_ldst() 64 regs->regs[RN_BITS(instr)] = addr; in do_alignment_finish_ldst() 75 /* ARMv7 Thumb-2 32-bit LDRD/STRD */ in do_alignment_ldrdstrd() 91 regs->regs[rd] = val; in do_alignment_ldrdstrd() 92 regs->regs[rd2] = val2; in do_alignment_ldrdstrd() 94 if (put_user(regs->regs[rd], (u32 __user *)addr) || in do_alignment_ldrdstrd() [all …]
|
/linux/tools/perf/util/ |
H A D | cs-etm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 24 /* PMU->type (32 bit), total # of CPUs (32 bit) */ 65 /* define fixed version 0 length - allow new format reader to read old files. */ 66 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1) 83 /* define fixed version 0 length - allow new format reader to read old files. */ 84 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1) 114 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors. 136 * table 6-12 Possible values for the TYPE field in an Exception instruction 137 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs. 192 * When working with per-thread scenarios the process under trace can [all …]
|
/linux/arch/arm/mach-omap2/ |
H A D | omap-headsmp.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * Copyright (C) 2009-2014 Texas Instruments, Inc. 58 .arch armv7-a 113 * bit 1 == Non-Secure Enable 114 * The Non-Secure banked register has not changed 116 * GIC restoration will cause a problem to CPU0 Non-Secure SW. 120 * 2) CPU1 must re-enable the GIC distributor on
|
H A D | sleep34xx.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 5 * Karthik Dasu <karthik-dp@ti.com> 9 * Richard Woodruff <r-woodruff2@ti.com> 57 * with non-Thumb-2-capable firmware. 86 .arch armv7-a 89 stmfd sp!, {r4 - r11, lr} @ save registers on stack 103 ldmfd sp!, {r4 - r11, pc} 115 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed 121 * - only the minimum set of functions gets copied to internal SRAM at boot 122 * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function [all …]
|
/linux/Documentation/devicetree/bindings/arm/tegra/ |
H A D | nvidia,tegra194-cbb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sumit Gupta <sumitg@nvidia.com> 15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various 20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC" 28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the 31 - For other initiators, the ERD is disabled. So, the access issuing 34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and [all …]
|
/linux/Documentation/arch/arm/samsung/ |
H A D | bootloader-interface.rst | 14 In the document "boot loader" means any of following: U-boot, proprietary 15 SBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before 19 1. Non-Secure mode 65 3. Other (regardless of secure/non-secure mode) 72 0x0908 Non-zero Secondary CPU boot up indicator 79 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other 81 MCPM - Multi-Cluster Power Management
|
/linux/drivers/perf/ |
H A D | arm_v7_pmu.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code. 5 * ARMv7 support: Jean Pihet <jpihet@mvista.com> 9 * by the ARMv7 Oprofile code. 11 * Cortex-A8 has up to 4 configurable performance counters and 13 * Cortex-A9 has up to 31 configurable performance counters and 31 * Common ARMv7 event types 53 * - all (taken) branch instructions, 54 * - instructions that explicitly write the PC, 55 * - exception generating instructions. [all …]
|
/linux/lib/raid6/ |
H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 2 obj-$(CONFIG_RAID6_PQ) += raid6_pq.o 4 raid6_pq-y += algos.o recov.o tables.o int1.o int2.o int4.o \ 7 raid6_pq-$(CONFIG_X86) += recov_ssse3.o recov_avx2.o mmx.o sse1.o sse2.o avx2.o avx512.o recov_avx512.o 8 raid6_pq-$(CONFIG_ALTIVEC) += altivec1.o altivec2.o altivec4.o altivec8.o \ 10 raid6_pq-$(CONFIG_KERNEL_MODE_NEON) += neon.o neon1.o neon2.o neon4.o neon8.o recov_neon.o recov_neon_inner.o 11 raid6_pq-$(CONFIG_S390) += s390vx8.o recov_s390xc.o 12 raid6_pq- [all...] |
/linux/arch/arm/boot/dts/amazon/ |
H A D | alpine.dtsi | 27 #include <dt-bindings/interrupt-controller/arm-gic.h> 30 #address-cells = <2>; 31 #size-cells = <2>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 enable-method = "al,alpine-smp"; 47 compatible = "arm,cortex-a15"; 50 clock-frequency = <1700000000>; 54 compatible = "arm,cortex-a15"; 57 clock-frequency = <1700000000>; [all …]
|
/linux/arch/arm/boot/compressed/ |
H A D | head.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * Copyright (C) 1996-2002 Russell King 12 #include "efi-header.S" 20 AR_CLASS( .arch armv7-a ) 21 M_CLASS( .arch armv7-m ) 101 kputc #'-' 105 kputc #'-' 110 kputc #'-' 154 * in little-endian form. 234 * Booting from Angel - need to enter SVC mode and disable [all …]
|
/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx7d.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 7 #include <dt-bindings/reset/imx7-reset.h> 18 clock-frequency = <996000000>; 19 operating-points-v2 = <&cpu0_opp_table>; 20 #cooling-cells = <2>; 21 nvmem-cells = <&fuse_grade>; 22 nvmem-cell-names = "speed_grade"; 26 compatible = "arm,cortex-a7"; 29 clock-frequency = <996000000>; 30 operating-points-v2 = <&cpu0_opp_table>; [all …]
|
/linux/net/netfilter/ |
H A D | nft_set_pipapo.h | 1 // SPDX-License-Identifier: GPL-2.0-only 8 /* Count of concatenated fields depends on count of 32-bit nftables registers */ 25 #define NFT_PIPAPO_GROUPS_PER_BYTE(f) (BITS_PER_BYTE / (f)->bb) 32 * crossing page boundaries on most architectures (x86-64 and MIPS huge pages, 33 * ARMv7 supersections, POWER "large" pages, SPARC Level 1 regions, etc.), which 34 * keeps performance nice in case kvmalloc() gives us non-contiguous areas. 39 #define NFT_PIPAPO_LT_SIZE_LOW NFT_PIPAPO_LT_SIZE_THRESHOLD - \ 44 (round_up((f)->groups / NFT_PIPAPO_GROUPS_PER_BYTE(f), sizeof(u32))) 46 (NFT_PIPAPO_GROUPS_PADDED_SIZE(f) - (f)->groups / \ 52 /* Each n-bit range maps to up to n * 2 rules */ [all …]
|