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/linux/Documentation/devicetree/bindings/pci/
H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm2712-pcie # Raspberry Pi 5
18 - brcm,bcm4908-pcie
19 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
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/linux/drivers/pci/pcie/
H A Daspm.c1 // SPDX-License-Identifier: GPL-2.0
44 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n"); in pci_save_ltr_state()
49 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
65 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
73 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pci_configure_aspm_l1ss()
78 pci_err(pdev, "unable to allocate ASPM L1SS save buffer (%pe)\n", in pci_configure_aspm_l1ss()
84 struct pci_dev *parent = pdev->bus->self; in pci_save_aspm_l1ss_state()
89 * If this is a Downstream Port, we never restore the L1SS state in pci_save_aspm_l1ss_state()
96 if (!pdev->l1ss || !parent->l1ss) in pci_save_aspm_l1ss_state()
107 cap = &save_state->cap.data[0]; in pci_save_aspm_l1ss_state()
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/linux/drivers/pci/controller/
H A Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
166 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
168 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
196 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX])
197 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA])
198 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1])
199 #define HARD_DEBUG(pcie) ((pcie)->cfg->offsets[PCIE_HARD_DEBUG])
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/linux/arch/x86/pci/
H A Dfixup.c1 // SPDX-License-Identifier: GPL-2.0
3 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
19 * i450NX -- Find and scan all secondary buses on all PXB's. in pci_fixup_i450nx()
24 dev_warn(&d->dev, "Searching for i450NX host bridges\n"); in pci_fixup_i450nx()
30 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, in pci_fixup_i450nx()
37 pcibios_last_bus = -1; in pci_fixup_i450nx()
44 * i450GX and i450KX -- Find and scan all secondary buses. in pci_fixup_i450gx()
49 dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno); in pci_fixup_i450gx()
51 pcibios_last_bus = -1; in pci_fixup_i450gx()
63 dev_warn(&d->dev, "Fixing base address flags\n"); in pci_fixup_umc_ide()
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/linux/drivers/misc/cardreader/
H A Drtsx_pcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
13 #include <linux/dma-mapping.h>
87 if (pcr->aspm_enabled == enable) in rtsx_comm_set_aspm()
90 if (pcr->aspm_mode == ASPM_MODE_CFG) { in rtsx_comm_set_aspm()
91 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rtsx_comm_set_aspm()
93 enable ? pcr->aspm_en : 0); in rtsx_comm_set_aspm()
94 } else if (pcr->aspm_mode == ASPM_MODE_REG) { in rtsx_comm_set_aspm()
95 if (pcr->aspm_en & 0x02) in rtsx_comm_set_aspm()
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/linux/drivers/pci/controller/dwc/
H A Dpcie-qcom-ep.c1 // SPDX-License-Identifier: GPL-2.0
27 #include "pcie-designware.h"
28 #include "pcie-qcom-common.h"
157 #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
167 * struct qcom_pcie_ep_cfg - Per SoC config struct
179 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
232 struct dw_pcie *pci = &pcie_ep->pci; in qcom_pcie_ep_core_reset()
233 struct device *dev = pci->dev; in qcom_pcie_ep_core_reset()
236 ret = reset_control_assert(pcie_ep->core_reset); in qcom_pcie_ep_core_reset()
244 ret = reset_control_deassert(pcie_ep->core_reset); in qcom_pcie_ep_core_reset()
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H A Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
296 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
301 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
306 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
309 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
316 if (icc_set_bw(pcie->icc_path, Mbps_to_icc(val), 0)) in tegra_pcie_icc_set()
317 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
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H A Dpcie-designware-host.c1 // SPDX-License-Identifier: GPL-2.0
21 #include "pcie-designware.h"
44 .name = "PCI-MSI",
66 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; in dw_handle_msi_irq()
79 generic_handle_domain_irq(pp->irq_domain, in dw_handle_msi_irq()
109 msi_target = (u64)pp->msi_data; in dw_pci_setup_msi_msg()
111 msg->address_lo = lower_32_bits(msi_target); in dw_pci_setup_msi_msg()
112 msg->address_hi = upper_32_bits(msi_target); in dw_pci_setup_msi_msg()
114 msg->data = d->hwirq; in dw_pci_setup_msi_msg()
116 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", in dw_pci_setup_msi_msg()
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/linux/include/linux/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
60 * The PCI interface treats multi-function devices as independent
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
86 return kobject_name(&slot->kobj); in pci_slot_name()
97 /* #0-5: standard PCI resources */
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
104 /* Device-specific resources */
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
171 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
173 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
181 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
182 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
183 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
185 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
190 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
193 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
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/linux/drivers/net/wireless/ath/ath10k/
H A Dwmi.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
29 * 1. Add new WMI commands ONLY within the specified range - 0x9000 - 0x9fff
45 * variable is already 4-byte aligned by virtue of being a u32
68 * There is no signed version of __le32, so for a temporary solution come
527 * for wmi_services is 64 as target is using only 4-bits of each 32-bit
533 __le32_to_cpu((wmi_svc_bmap)[((svc_id) - (len)) / 28]) & \
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