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/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-edp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-edp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 to a Embedded DisplayPort AUX bus (see display/dp-aux-bus.yaml) without
17 board, either for second-sourcing purposes or to support multiple SKUs
51 :<T1>:<T2>: :<--T10-->:<T11>:<T12>:
52 : +-----------------------+---------+---------+
53 eDP -----------+ Black video | Src vid | Blk vid +
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dconn.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
46 static const u8 hpd[] = { 0x07, 0x08, 0x51, 0x52, 0x5e, 0x5f, 0x60 }; in nvkm_conn_ctor() local
47 struct nvkm_gpio *gpio = disp->engine.subdev.device->gpio; in nvkm_conn_ctor()
51 conn->disp = disp; in nvkm_conn_ctor()
52 conn->index = index; in nvkm_conn_ctor()
53 conn->info = *info; in nvkm_conn_ctor()
54 conn->info.hpd = DCB_GPIO_UNUSED; in nvkm_conn_ctor()
56 CONN_DBG(conn, "type %02x loc %d hpd %02x dp %x di %x sr %x lcdid %x", in nvkm_conn_ctor()
57 info->type, info->location, info->hpd, info->dp, in nvkm_conn_ctor()
58 info->di, info->sr, info->lcdid); in nvkm_conn_ctor()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_hpd.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28 * This file implements functions that manage basic HPD components such as gpio.
29 * It also provides wrapper functions to execute HPD related programming. This
30 * file only manages basic HPD functionality. It doesn't manage detection or
31 * feature or signal specific HPD behaviors.
40 dal_gpio_lock_pin(link->hpd_gpio); in link_get_hpd_state()
41 dal_gpio_get_value(link->hpd_gpio, &state); in link_get_hpd_state()
42 dal_gpio_unlock_pin(link->hpd_gpio); in link_get_hpd_state()
49 struct link_encoder *encoder = link->link_enc; in link_enable_hpd()
51 if (encoder != NULL && encoder->funcs->enable_hpd != NULL) in link_enable_hpd()
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/linux/Documentation/userspace-api/media/cec/
H A Dcec-ioc-dqevent.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 CEC_DQEVENT - Dequeue a CEC event
35 non-blocking mode and no event is pending, then it will return -1 and
38 The internal event queues are per-filehandle and per-event type. If
39 there is no more room in a queue then the last event is overwritten with
43 two :ref:`CEC_EVENT_STATE_CHANGE <CEC-EVENT-STATE-CHANGE>` events with
51 .. flat-table:: struct cec_event_state_change
52 :header-rows: 0
53 :stub-columns: 0
56 * - __u16
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/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_hpd.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 hpd->shifts->field_name, hpd->masks->field_name
41 hpd->base.base.ctx
43 (hpd->regs->reg)
50 dal_hw_gpio_destruct(&pin->base); in dal_hw_hpd_destruct()
56 struct hw_hpd *hpd = HW_HPD_FROM_BASE(*ptr); in dal_hw_hpd_destroy() local
58 dal_hw_hpd_destruct(hpd); in dal_hw_hpd_destroy()
60 kfree(hpd); in dal_hw_hpd_destroy()
69 struct hw_hpd *hpd = HW_HPD_FROM_BASE(ptr); in dal_hw_hpd_get_value() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
H A Dhw_factory_dcn401.c1 // SPDX-License-Identifier: MIT
29 #define block HPD
90 // add a dummy entry for cases no such port
97 // add a dummy entry for cases no such port
117 // add a dummy entry for cases no such port
124 // add a dummy entry for cases no such port
188 generic->regs = &generic_regs[en]; in define_generic_registers()
189 generic->shifts = &generic_shift[en]; in define_generic_registers()
190 generic->masks = &generic_mask[en]; in define_generic_registers()
191 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_combios.c3 * Copyright 2007-8 Advanced Micro Devices, Inc.
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
133 struct radeon_device *rdev = dev->dev_private; in combios_get_table_offset()
137 if (!rdev->bios) in combios_get_table_offset()
362 size = RBIOS8(rdev->bios_header_start + 0x6); in combios_get_table_offset()
365 offset = RBIOS16(rdev->bios_header_start + check_offset); in combios_get_table_offset()
379 raw = rdev->bios + edid_info; in radeon_combios_check_hardcoded_edid()
388 rdev->mode_info.bios_hardcoded_edid = edid; in radeon_combios_check_hardcoded_edid()
396 return drm_edid_duplicate(drm_edid_raw(rdev->mode_info.bios_hardcoded_edid)); in radeon_bios_get_hardcoded_edid()
447 if (rdev->family == CHIP_RS300 || in combios_setup_i2c_bus()
[all …]
H A Drs600.c18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
39 #include <linux/io-64-nonatomic-lo-hi.h>
59 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
84 * avivo_wait_for_vblank - vblank wait asic callback.
89 * Wait for vblank on the requested crtc (r5xx-r7xx).
95 if (crtc >= rdev->num_crtc) in avivo_wait_for_vblank()
121 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
122 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in rs600_page_flip()
123 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
128 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
61 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
65 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW
118 // for example, 1080p -> 8K is 4.0, or 4000 raw value
126 // for example, 8K -> 1080p is 0.25, or 250 raw value
138 * DOC: color-management-caps
143 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
150 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
166 * struct dpp_color_caps - color pipeline capabilities for display pipe and
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_factory_dcn32.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
49 #define block HPD
111 // add a dummy entry for cases no such port
132 // add a dummy entry for cases no such port
196 generic->regs = &generic_regs[en]; in define_generic_registers()
197 generic->shifts = &generic_shift[en]; in define_generic_registers()
198 generic->masks = &generic_mask[en]; in define_generic_registers()
199 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
208 switch (pin->id) { in define_ddc_registers()
210 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
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/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
19 - samsung,exynos4212-hdmi
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_factory_dce120.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
42 #define block HPD
135 switch (pin->id) { in define_ddc_registers()
137 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
138 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
141 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
142 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
149 ddc->shifts = &ddc_shift; in define_ddc_registers()
150 ddc->masks = &ddc_mask; in define_ddc_registers()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v6_0.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
94 (0x13830 - 0x7030) >> 2,
101 uint32_t hpd; member
107 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
117 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
122 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
127 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
132 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
141 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
[all …]
H A Ddce_v8_0.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
82 (0x13830 - 0x7030) >> 2,
89 uint32_t hpd; member
95 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
129 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_rreg()
[all …]
H A Ddce_v10_0.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
90 uint32_t hpd; member
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
150 switch (adev->asic_type) { in dce_v10_0_init_golden_registers()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce80/
H A Dhw_factory_dce80.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
122 switch (pin->id) { in define_ddc_registers()
124 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
128 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
129 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
136 ddc->shifts = &ddc_shift; in define_ddc_registers()
137 ddc->masks = &ddc_mask; in define_ddc_registers()
143 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); in define_hpd_registers() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce60/
H A Dhw_factory_dce60.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
122 switch (pin->id) { in define_ddc_registers()
124 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
128 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
129 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
136 ddc->shifts = &ddc_shift; in define_ddc_registers()
137 ddc->masks = &ddc_mask; in define_ddc_registers()
143 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); in define_hpd_registers() local
145 hpd->regs = &hpd_regs[en]; in define_hpd_registers()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_factory_dcn10.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43 #define block HPD
155 generic->regs = &generic_regs[en]; in define_generic_registers()
156 generic->shifts = &generic_shift[en]; in define_generic_registers()
157 generic->masks = &generic_mask[en]; in define_generic_registers()
158 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
167 switch (pin->id) { in define_ddc_registers()
169 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
170 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/
H A Dhw_factory_dce110.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
118 switch (pin->id) { in define_ddc_registers()
120 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
121 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
124 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
132 ddc->shifts = &ddc_shift; in define_ddc_registers()
133 ddc->masks = &ddc_mask; in define_ddc_registers()
139 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); in define_hpd_registers() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_factory_dcn21.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
47 #define block HPD
163 generic->regs = &generic_regs[en]; in define_generic_registers()
164 generic->shifts = &generic_shift[en]; in define_generic_registers()
165 generic->masks = &generic_mask[en]; in define_generic_registers()
166 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
175 switch (pin->id) { in define_ddc_registers()
177 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
178 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-trogdor-homestar-r2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "sc7180-trogdor.dtsi"
11 #include "sc7180-trogdor-ti-sn65dsi86.dtsi"
12 #include "sc7180-trogdor-homestar.dtsi"
16 compatible = "google,homestar-rev2","google,homestar-rev23", "qcom,sc7180";
20 /delete-property/hpd-gpios;
21 no-hpd;
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_factory_dcn20.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
49 #define block HPD
187 switch (pin->id) { in define_ddc_registers()
189 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
190 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
193 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
194 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
201 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
202 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
56 #define block HPD
192 generic->regs = &generic_regs[en]; in define_generic_registers()
193 generic->shifts = &generic_shift[en]; in define_generic_registers()
194 generic->masks = &generic_mask[en]; in define_generic_registers()
195 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
204 switch (pin->id) { in define_ddc_registers()
206 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
207 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
210 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
53 #define block HPD
184 generic->regs = &generic_regs[en]; in define_generic_registers()
185 generic->shifts = &generic_shift[en]; in define_generic_registers()
186 generic->masks = &generic_mask[en]; in define_generic_registers()
187 generic->base.regs = &generic_regs[en].gpio; in define_generic_registers()
196 switch (pin->id) { in define_ddc_registers()
198 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
199 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
202 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
23 enable-gpios:
27 suspend-gpios:
31 no-hpd:
34 Set if the HPD line on the bridge isn't hooked up to anything or is
37 vccio-supply:
40 vpll-supply:
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