xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sm7150-tlmm.yaml (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm7150-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM7150 TLMM pin controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Danila Tikhonov <danila@jiaxyga.com>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm SM7150 SoC.
15
16allOf:
17  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sm7150-tlmm
22
23  reg:
24    maxItems: 3
25
26  reg-names:
27    items:
28      - const: west
29      - const: north
30      - const: south
31
32  interrupts:
33    maxItems: 1
34
35  gpio-reserved-ranges:
36    minItems: 1
37    maxItems: 60
38
39  gpio-line-names:
40    maxItems: 119
41
42patternProperties:
43  "-state$":
44    oneOf:
45      - $ref: "#/$defs/qcom-sm7150-tlmm-state"
46      - patternProperties:
47          "-pins$":
48            $ref: "#/$defs/qcom-sm7150-tlmm-state"
49        additionalProperties: false
50
51$defs:
52  qcom-sm7150-tlmm-state:
53    type: object
54    description:
55      Pinctrl node's client devices use subnodes for desired pin configuration.
56      Client device subnodes use below standard properties.
57    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
58    unevaluatedProperties: false
59
60    properties:
61      pins:
62        description:
63          List of gpio pins affected by the properties specified in this
64          subnode.
65        items:
66          oneOf:
67            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
68            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
69                      sdc2_cmd, sdc2_data, ufs_reset ]
70        minItems: 1
71        maxItems: 36
72
73      function:
74        description:
75          Specify the alternative function to be configured for the specified
76          pins.
77
78        enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
79                atest_tsens2, atest_usb1, atest_usb2, cam_mclk, cci_async,
80                cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
81                cci_timer4, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2,
82                ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0,
83                gp_pdm1, gp_pdm2, gps_tx, jitter_bist, ldo_en, ldo_update,
84                m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
85                mdp_vsync3, mss_lte, nav_pps_in, nav_pps_out, pa_indicator,
86                pci_e, phase_flag, pll_bist, pll_bypassnl, pll_reset, pri_mi2s,
87                pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
88                qlink_request, qua_mi2s, qup00, qup01, qup02, qup03, qup04,
89                qup10, qup11, qup12, qup13, qup14, qup15, sd_write, sdc40,
90                sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, ter_mi2s,
91                tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsif1_clk, tsif1_data,
92                tsif1_en, tsif1_error, tsif1_sync, tsif2_clk, tsif2_data,
93                tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data,
94                uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
95                uim2_reset, uim_batt, usb_phy, vfr_1, vsense_trigger,
96                wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk,
97                wsa_data ]
98
99    required:
100      - pins
101
102required:
103  - compatible
104  - reg
105  - reg-names
106
107unevaluatedProperties: false
108
109examples:
110  - |
111    #include <dt-bindings/interrupt-controller/arm-gic.h>
112
113    tlmm: pinctrl@3500000 {
114        compatible = "qcom,sm7150-tlmm";
115        reg = <0x03500000 0x300000>,
116              <0x03900000 0x300000>,
117              <0x03d00000 0x300000>;
118        reg-names = "west", "north", "south";
119        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
120        gpio-ranges = <&tlmm 0 0 120>;
121        gpio-controller;
122        #gpio-cells = <2>;
123        interrupt-controller;
124        #interrupt-cells = <2>;
125        wakeup-parent = <&pdc>;
126
127        gpio-wo-state {
128            pins = "gpio1";
129            function = "gpio";
130        };
131
132        uart-w-state {
133            rx-pins {
134                pins = "gpio44";
135                function = "qup12";
136                bias-pull-up;
137            };
138
139            tx-pins {
140                pins = "gpio45";
141                function = "qup12";
142                bias-disable;
143            };
144        };
145    };
146...
147