| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
27 -- Additional SoC-specific NAND controller properties --
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| /linux/drivers/mtd/nand/raw/ |
| H A D | sm_common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
9 /* Full oob structure as written on the flash */
21 /* one sector is always 512 bytes, but it can consist of two nand pages */
24 /* oob area is also 16 bytes, but might be from two pages */
27 /* This is maximum zone size, and all devices that have more that one zone
28 have this size */
31 /* support for small page nand */
39 static inline int sm_sector_valid(struct sm_oob *oob) in sm_sector_valid() argument
41 return hweight16(oob->data_status) >= 5; in sm_sector_valid()
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| H A D | omap2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-sw-bch.h>
21 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
131 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
145 struct nand_chip nand; member
172 /* NAND ready gpio */
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| H A D | nandsim.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * NAND flash simulator.
9 * Note: NS means "NAND Simulator".
132 MODULE_PARM_DESC(id_bytes, "The ID bytes returned by NAND Flash 'read ID' command");
133 MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufact…
134 MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID…
135 MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command (obsolete…
136 MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command (obsolet…
139 MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
142 MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
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| H A D | cadence-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence NAND flash controller driver
12 #include <linux/dma-mapping.h>
26 * - PIO - can work in master or slave DMA
27 * - CDMA - needs Master DMA for accessing command descriptors.
28 * - Generic mode - can use only slave DMA.
31 * on NAND flash memory. Driver uses CDMA mode for
115 /* Size of last data sector. */
117 /* Size of not-last data sector. */
142 /* Transferred data block size for the slave DMA module. */
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| H A D | tegra_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20) argument
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4) argument
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0) argument
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
213 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_rs_ecc()
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| H A D | sh_flctl.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH FLCTL nand controller
8 * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
16 #include <linux/dma-mapping.h>
37 return -ERANGE; in flctl_4secc_ooblayout_sp_ecc()
39 oobregion->offset = 0; in flctl_4secc_ooblayout_sp_ecc()
40 oobregion->length = chip->ecc.bytes; in flctl_4secc_ooblayout_sp_ecc()
49 return -ERANGE; in flctl_4secc_ooblayout_sp_free()
51 oobregion->offset = 12; in flctl_4secc_ooblayout_sp_free()
52 oobregion->length = 4; in flctl_4secc_ooblayout_sp_free()
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| H A D | mtk_nand.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * MTK NAND Flash controller driver.
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mtk.h>
21 /* NAND controller register definition */
89 #define MTK_NAME "mtk-nand"
117 * FDM: region used to store free OOB data
126 struct nand_chip nand; member
161 * supported spare size of each IP.
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| H A D | denali.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * NAND Flash Controller Device Driver
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
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| H A D | r852.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
31 MODULE_PARM_DESC(debug, "Debug level (0-2)");
36 uint8_t reg = readb(dev->mmio + address); in r852_read_reg()
44 writeb(value, dev->mmio + address); in r852_write_reg()
51 uint32_t reg = le32_to_cpu(readl(dev->mmio + address)); in r852_read_reg_dword()
59 writel(cpu_to_le32(value), dev->mmio + address); in r852_write_reg_dword()
73 dev->dma_usable = (r852_read_reg(dev, R852_DMA_CAP) & in r852_dma_test()
76 if (!dev->dma_usable) in r852_dma_test()
81 dev->dma_usable = 0; in r852_dma_test()
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| H A D | stm32_fmc2_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
28 /* ECC step size */
37 /* Max requests done for a 8k nand page size */
256 struct stm32_fmc2_nand nand; member
294 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); in stm32_fmc2_nfc_timings_init()
295 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); in stm32_fmc2_nfc_timings_init() local
296 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_nfc_timings_init()
300 regmap_update_bits(nfc->regmap, FMC2_PCR, in stm32_fmc2_nfc_timings_init()
302 FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) | in stm32_fmc2_nfc_timings_init()
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| /linux/arch/mips/boot/dts/brcm/ |
| H A D | bcm97xxx-nand-cs1-bch24.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 &nand {
6 nand-on-flash-bbt;
8 nand-ecc-strength = <24>;
9 nand-ecc-step-size = <1024>;
10 brcm,nand-oob-sector-size = <27>;
13 compatible = "fixed-partitions";
14 #address-cells = <1>;
15 #size-cells = <1>;
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| H A D | bcm97xxx-nand-cs1-bch4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 &nand {
6 nand-on-flash-bbt;
8 nand-ecc-strength = <4>;
9 nand-ecc-step-size = <512>;
10 brcm,nand-oob-sector-size = <16>;
13 compatible = "fixed-partitions";
14 #address-cells = <1>;
15 #size-cells = <1>;
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| /linux/arch/arm/boot/dts/broadcom/ |
| H A D | bcm963138dvt.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
16 stdout-path = &serial0;
35 brcm,wp-not-connected;
40 nand-ecc-strength = <4>;
41 nand-ecc-step-size = <512>;
42 brcm,nand-oob-sector-size = <16>;
43 nand-on-flash-bbt;
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| H A D | bcm958300k.dts | 33 /dts-v1/;
35 #include "bcm-cygnus.dtsi"
47 stdout-path = "serial0:115200n8";
64 nand@1 {
67 nand-on-flash-bbt;
69 #address-cells = <1>;
70 #size-cells = <1>;
72 nand-ecc-strength = <24>;
73 nand-ecc-step-size = <1024>;
75 brcm,nand-oob-sector-size = <27>;
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| H A D | bcm958305k.dts | 33 /dts-v1/;
35 #include "bcm-cygnus.dtsi"
47 stdout-path = "serial0:115200n8";
72 nand@1 {
75 nand-on-flash-bbt;
77 #address-cells = <1>;
78 #size-cells = <1>;
80 nand-ecc-strength = <24>;
81 nand-ecc-step-size = <1024>;
83 brcm,nand-oob-sector-size = <27>;
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| H A D | bcm911360_entphn.dts | 33 /dts-v1/;
35 #include "bcm-cygnus.dtsi"
36 #include "dt-bindings/input/input.h"
47 stdout-path = "serial0:115200n8";
50 gpio-keys {
51 compatible = "gpio-keys";
53 button-hook {
74 assigned-clocks =
77 assigned-clock-rates = <525000000>, <300000000>;
86 nand@1 {
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| H A D | bcm958625-meraki-mx6x-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 #include "bcm-nsp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
14 pwm-leds {
15 compatible = "pwm-leds";
17 led-1 {
21 max-brightness = <255>;
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| /linux/drivers/mtd/ |
| H A D | sm_ftl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
16 #include <linux/mtd/nand-ecc-sw-hamming.h>
17 #include "nand/raw/sm_common.h"
31 MODULE_PARM_DESC(debug, "Debug level (0-2)");
34 /* ------------------- sysfs attributes ---------------------------------- */
47 strncpy(buf, sm_attr->data, sm_attr->len); in sm_attr_show()
48 return sm_attr->len; in sm_attr_show()
61 vendor = kstrndup(ftl->cis_buffer + SM_CIS_VENDOR_OFFSET, in sm_create_sysfs_attributes()
62 SM_SMALL_PAGE - SM_CIS_VENDOR_OFFSET, GFP_KERNEL); in sm_create_sysfs_attributes()
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| H A D | nftlcore.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux driver for NAND Flash Translation Layer
6 * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
40 if (!mtd_type_is_nand(mtd) || mtd->size > UINT_MAX) in nftl_add_mtd()
43 if (memcmp(mtd->name, "DiskOnChip", 10)) in nftl_add_mtd()
46 pr_debug("NFTL: add_mtd for %s\n", mtd->name); in nftl_add_mtd()
53 nftl->mbd.mtd = mtd; in nftl_add_mtd()
54 nftl->mbd.devnum = -1; in nftl_add_mtd()
56 nftl->mbd.tr = tr; in nftl_add_mtd()
67 nftl->cylinders = 1024; in nftl_add_mtd()
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| H A D | ssfdc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
54 unsigned long size; member
60 /* Must be ordered by size */
73 static int get_chs(unsigned long size, unsigned short *cyl, unsigned char *head, in get_chs() argument
80 while (chs_table[k].size > 0 && size > chs_table[k].size) in get_chs()
83 if (chs_table[k].size > 0) { in get_chs()
96 /* These bytes are the signature for the CIS/IDI sector */
101 /* Read and check for a valid CIS sector */
109 cis_sector = -1; in get_valid_cis_sector()
116 * Look for CIS/IDI sector on the first GOOD block (give up after 4 bad in get_valid_cis_sector()
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| H A D | inftlmount.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * inftlmount.c -- INFTL mount code with extensive checks.
6 * Copyright © 2002-2003, Greg Ungerer (gerg@snapgear.com)
34 //struct inftl_oob oob; in find_boot_record()
37 struct INFTLMediaHeader *mh = &inftl->MediaHdr; in find_boot_record()
38 struct mtd_info *mtd = inftl->mbd.mtd; in find_boot_record()
49 inftl->EraseSize = inftl->mbd.mtd->erasesize; in find_boot_record()
50 inftl->nb_blocks = (u32)inftl->mbd.mtd->size / inftl->EraseSize; in find_boot_record()
52 inftl->MediaUnit = BLOCK_NIL; in find_boot_record()
55 for (block = 0; block < inftl->nb_blocks; block++) { in find_boot_record()
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| /linux/arch/arm64/boot/dts/broadcom/stingray/ |
| H A D | bcm958742-base.dtsi | 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 #include "stingray-board-base.dtsi"
37 compatible = "regulator-gpio";
38 regulator-name = "sdio0_vddo_ctrl_reg";
39 regulator-type = "voltage";
40 regulator-min-microvolt = <1800000>;
41 regulator-max-microvolt = <3300000>;
48 compatible = "regulator-gpio";
49 regulator-name = "sdio1_vddo_ctrl_reg";
50 regulator-type = "voltage";
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| /linux/drivers/mtd/nand/ |
| H A D | ecc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
15 * - external: The ECC engine is outside the NAND pipeline, typically this
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
24 * Some NAND chips can correct themselves the data.
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