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/linux/Documentation/devicetree/bindings/mtd/
H A Dnand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
16 This file covers the generic description of a NAND chip. It implies that the
17 bus interface should not be taken into account: both raw NAND devices and
18 SPI-NAND devices are concerned by this description.
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/linux/drivers/mtd/nand/
H A Decc-sw-bch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file provides ECC correction for more than 1 bit per block of data,
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
19 * @nand: NAND device
21 * @code: Output buffer with ECC
23 int nand_ecc_sw_bch_calculate(struct nand_device *nand, in nand_ecc_sw_bch_calculate() argument
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
29 memset(code, 0, engine_conf->code_size); in nand_ecc_sw_bch_calculate()
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H A Decc-sw-hamming.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains an ECC algorithm that detects and corrects 1 bit
9 * Completely replaces the previous ECC implementation which was written by:
14 * can be found in Documentation/driver-api/mtd/nand_ecc.rst
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/nand-ecc-sw-hamming.h>
75 * addressbits is a lookup table to filter out the bits from the xor-ed
76 * ECC data that identify the faulty location.
294 * leaving it out gives slightly worse results. No idea why, probably in ecc_sw_hamming_calculate()
307 * Finally calculate the ECC bits. in ecc_sw_hamming_calculate()
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H A Decc-mtk.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * MTK ECC controller driver.
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-mtk.h>
71 /* ecc strength that each IP supports */
126 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
129 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
143 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
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/linux/drivers/mtd/nand/raw/ingenic/
H A Dingenic_ecc.c1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx ECC common code
19 * ingenic_ecc_calculate() - calculate ECC for a data buffer
20 * @ecc: ECC device.
21 * @params: ECC parameters.
23 * @ecc_code: output buffer with ECC.
25 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
28 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
32 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
36 * ingenic_ecc_correct() - detect and correct bit errors
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H A Dingenic_nand_drv.c1 // SPDX-License-Identifier: GPL-2.0
3 * Ingenic JZ47xx NAND driver
23 #include <linux/jz4780-nemc.h>
27 #define DRV_NAME "ingenic-nand"
44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
78 return -ERANGE; in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
81 oobregion->offset = 12; in qi_lb60_ooblayout_ecc()
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/linux/drivers/mtd/nand/raw/
H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
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H A Dsocrates_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * socrates_nand_write_buf - write buffer to chip
34 * @this: NAND chip object
45 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
52 * socrates_nand_read_buf - read chip data into buffer
53 * @this: NAND chip object
66 out_be32(host->io_base, val); in socrates_nand_read_buf()
68 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
74 * socrates_nand_read_byte - read one byte from the chip
85 * Hardware specific access to control-lines
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H A Dxway_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
14 /* nand registers */
18 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */
19 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
24 * nand commands
25 * The pins of the NAND chip are selected based on the address bits of the
26 * "register" read and write. There are no special registers, but an
41 /* we need to tel the ebu which addr we mapped the nand to */
45 /* we need to tell the EBU that we have nand attached and set it up properly */
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H A Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
150 * struct anand - Defines the NAND chip related information
151 * @node: Used to store NAND chips into a list
152 * @chip: NAND chip information structure
153 * @rb: Ready-busy line
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H A Dcadence-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence NAND flash controller driver
12 #include <linux/dma-mapping.h>
26 * - PIO - can work in master or slave DMA
27 * - CDMA - needs Master DMA for accessing command descriptors.
28 * - Generic mode - can use only slave DMA.
31 * on NAND flash memory. Driver uses CDMA mode for
90 /* Command Engine threads state. */
93 /* Command Engine interrupt thread error status. */
95 /* Command Engine interrupt thread error enable. */
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H A Dstm32_fmc2_nand.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
28 /* ECC step size */
37 /* Max requests done for a 8k nand page size */
43 /* Max ECC buffer length */
256 struct stm32_fmc2_nand nand; member
295 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); in stm32_fmc2_nfc_timings_init()
296 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); in stm32_fmc2_nfc_timings_init() local
297 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_nfc_timings_init()
301 regmap_update_bits(nfc->regmap, FMC2_PCR, in stm32_fmc2_nfc_timings_init()
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H A Dr852.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
14 /* nand interface + ecc
15 byte write/read does one cycle on nand data lines.
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
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H A Dorion_nand.c2 * NAND support for Marvell Orion SoC platforms
22 #include <linux/platform_data/mtd-orion_nand.h>
40 offs = (1 << board->cle); in orion_nand_cmd_ctrl()
42 offs = (1 << board->ale); in orion_nand_cmd_ctrl()
46 if (nc->options & NAND_BUSWIDTH_16) in orion_nand_cmd_ctrl()
49 writeb(cmd, nc->legacy.IO_ADDR_W + offs); in orion_nand_cmd_ctrl()
54 void __iomem *io_base = chip->legacy.IO_ADDR_R; in orion_nand_read_buf()
62 len--; in orion_nand_read_buf()
68 * Since GCC has no proper constraint (PR 43518) in orion_nand_read_buf()
88 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in orion_nand_attach_chip()
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H A Dau1550nd.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <asm/mach-au1x00/au1000.h>
16 #include <asm/mach-au1x00/au1550nd.h>
33 * au_write_buf - write buffer to chip
34 * @this: NAND chip object
48 writeb(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf()
54 * au_read_buf - read chip data into buffer
55 * @this: NAND chip object
69 p[i] = readb(ctx->base + MEM_STNAND_DATA); in au_read_buf()
75 * au_write_buf16 - write buffer to chip
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H A Dr852.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
31 MODULE_PARM_DESC(debug, "Debug level (0-2)");
36 uint8_t reg = readb(dev->mmio + address); in r852_read_reg()
44 writeb(value, dev->mmio + address); in r852_write_reg()
51 uint32_t reg = le32_to_cpu(readl(dev->mmio + address)); in r852_read_reg_dword()
59 writel(cpu_to_le32(value), dev->mmio + address); in r852_write_reg_dword()
73 dev->dma_usable = (r852_read_reg(dev, R852_DMA_CAP) & in r852_dma_test()
76 if (!dev->dma_usable) in r852_dma_test()
81 dev->dma_usable = 0; in r852_dma_test()
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H A Ddiskonchip.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * converted to the generic Reed-Solomon library by Thomas Gleixner <tglx@linutronix.de>
16 * Interface to generic NAND code for M-Systems DiskOnChip devices
79 /* This is the ecc value computed by the HW ecc generator upon writing an empty
85 #define DoC_is_MillenniumPlus(doc) ((doc)->ChipID == DOC_ChipID_DocMilPlus16 || (doc)->ChipID == DO…
86 #define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil)
87 #define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k)
115 /* Sector size for HW ECC */
129 * Reed-Solomon library code.
133 * of the generic Reed-Solomon library. tglx
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H A Dmeson_nand.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Amlogic Meson Nand Flash Controller Driver
10 #include <linux/dma-mapping.h>
13 #include <linux/clk-provider.h>
84 #define ECC_CHECK_RETURN_FF (-1)
101 /* nand flash controller delay 3 ns */
124 struct nand_chip nand; member
258 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand) in to_meson_nand() argument
260 return container_of(nand, struct meson_nfc_nand_chip, nand); in to_meson_nand()
263 static void meson_nfc_select_chip(struct nand_chip *nand, int chip) in meson_nfc_select_chip() argument
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H A Dqcom_nandc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-qpic-common.h>
21 * NAND special boot partitions
24 * by ECC (value in pages)
26 * by ECC (value in pages)
57 * NAND chip structure
62 * @chip: base NAND chip structure
67 * protected by ECC
71 * of a page, consisting of all data, ecc, spare
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H A Dmpc5121_nfc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
127 return in_be16(prv->regs + reg); in nfc_read()
136 out_be16(prv->regs + reg, val); in nfc_write()
167 /* Send data from NFC buffers to NAND flash */
175 /* Receive data from NAND flash */
183 /* Receive ID from NAND flash */
191 /* Receive status from NAND flash */
207 wake_up(&prv->irq_waitq); in mpc5121_nfc_irq()
221 rv = wait_event_timeout(prv->irq_waitq, in mpc5121_nfc_done()
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/linux/drivers/spi/
H A Dspi-qpic-snand.c2 * SPDX-License-Identifier: GPL-2.0
15 #include <linux/dma-mapping.h>
22 #include <linux/mtd/nand-qpic-common.h>
31 /* QSPI NAND config reg bits */
69 * ECC state struct
70 * @corrected: ECC corrected
72 * @failed: ECC failed
105 struct qpic_ecc *ecc; member
131 snandc->regs->read_location0 = locreg_val; in qcom_spi_set_read_loc_first()
133 snandc->regs->read_location1 = locreg_val; in qcom_spi_set_read_loc_first()
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/linux/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
20 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
27 * Add Programmable Multibit ECC support for various AT91 SoC
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
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/linux/arch/mips/boot/dts/ingenic/
H A Dci20.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/clock/ingenic,tcu.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/regulator/active-semi,8865-regulator.h>
22 stdout-path = &uart4;
31 gpio-keys {
32 compatible = "gpio-keys";
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/linux/Documentation/driver-api/mtd/
H A Dnand_ecc.rst2 NAND Error-correction Code
8 Having looked at the linux mtd/nand Hamming software ECC engine driver
11 After that the speed was increased by 35-40%.
22 NAND flash (at least SLC one) typically has sectors of 256 bytes.
23 However NAND flash is not extremely reliable so some error detection
31 As I said before the ecc calculation is performed on sectors of 256
41 Back to ecc.
63 - cp0 is the parity that belongs to all bit0, bit2, bit4, bit6.
69 - cp2 is the parity over bit0, bit1, bit4 and bit5
70 - cp3 is the parity over bit2, bit3, bit6 and bit7.
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
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