Searched +full:nand +full:- +full:bcm6368 (Results 1 – 6 of 6) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.03 #include "dt-bindings/clock/bcm6368-clock.h"4 #include "dt-bindings/reset/bcm6368-reset.h"7 #address-cells = <1>;8 #size-cells = <1>;9 compatible = "brcm,bcm6368";12 #address-cells = <1>;13 #size-cells = <0>;15 mips-hpt-frequency = <200000000>;31 periph_osc: periph-osc {[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include "dt-bindings/clock/bcm6362-clock.h"4 #include "dt-bindings/reset/bcm6362-reset.h"5 #include "dt-bindings/soc/bcm6362-pm.h"8 #address-cells = <1>;9 #size-cells = <1>;13 #address-cells = <1>;14 #size-cells = <0>;16 mips-hpt-frequency = <200000000>;32 periph_osc: periph-osc {[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include "dt-bindings/clock/bcm6328-clock.h"4 #include "dt-bindings/reset/bcm6328-reset.h"5 #include "dt-bindings/soc/bcm6328-pm.h"8 #address-cells = <1>;9 #size-cells = <1>;13 #address-cells = <1>;14 #size-cells = <0>;16 mips-hpt-frequency = <160000000>;32 periph_osc: periph-osc {[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include "dt-bindings/clock/bcm63268-clock.h"4 #include "dt-bindings/reset/bcm63268-reset.h"5 #include "dt-bindings/soc/bcm63268-pm.h"8 #address-cells = <1>;9 #size-cells = <1>;13 #address-cells = <1>;14 #size-cells = <0>;16 mips-hpt-frequency = <200000000>;32 periph_osc: periph-osc {[all …]
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Broadcom STB NAND Controller10 - Brian Norris <computersforpeace@gmail.com>11 - Kamal Dasu <kdasu.kdev@gmail.com>14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND15 flash chips. It has a memory-mapped register interface for both control25 -- Additional SoC-specific NAND controller properties --27 The NAND controller is integrated differently on the variety of SoCs on which[all …]
1 * Broadcom STB NAND Controller3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND4 flash chips. It has a memory-mapped register interface for both control15 - compatible : May contain an SoC-specific compatibility string (see below)16 to account for any SoC-specific hardware bits that may be19 the core NAND controller, of the following form:21 string, like "brcm,brcmnand-v7.0"23 brcm,brcmnand-v2.124 brcm,brcmnand-v2.225 brcm,brcmnand-v4.0[all …]