Searched full:mux_reg (Results 1 – 25 of 42) sorted by relevance
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| /freebsd/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | nxp,imx95-scmi-pinctrl.yaml | 29 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
38 "mux_reg" indicates the offset of mux register.
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | fsl,imx8mm-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
44 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imx8mn-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
44 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imx8mp-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
44 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imx8mq-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
44 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imx93-pinctrl.yaml | 38 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
47 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imxrt1050.yaml | 36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
45 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imxrt1170.yaml | 36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
45 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imx8m-pinctrl.yaml | 39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imx9-pinctrl.yaml | 40 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imx7d-pinctrl.yaml | 44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
53 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imx6ul-pinctrl.yaml | 40 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "mux_reg" indicates the offset of mux register.
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| H A D | fsl,imx6sx-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| H A D | fsl,imx6sll-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| H A D | fsl,imx6ul-pinctrl.txt | 10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| H A D | fsl,imx7d-pinctrl.txt | 32 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| H A D | fsl,imx-pinctrl.txt | 26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx_iomux.c | 92 uint32_t mux_reg; member
163 WR4(sc, cfg->mux_reg, cfg->mux_val | sion); in iomux_configure_pins()
173 name, cfg->mux_reg, cfg->mux_val | sion, in iomux_configure_pins()
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6ull-pinfunc-snvs.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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| H A D | imx6ull-pinfunc.h | 12 * <mux_reg conf_reg input_reg mux_mode input_val>
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| H A D | imx25-pinfunc.h | 13 * <mux_reg conf_reg input_reg mux_mode input_val>
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8mq-pinfunc.h | 12 * <mux_reg conf_reg input_reg mux_mode input_val>
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| H A D | imx93-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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| H A D | imx8mm-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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| H A D | imx8mn-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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