Searched full:multisynth (Results 1 – 4 of 4) sorted by relevance
103 0 - use multisynth N for this output, where N is the output number104 1 - use either multisynth 0 (if output number is 0-3) or multisynth 4114 silabs,multisynth-source:118 Source PLL A (0) or B (1) for the corresponding multisynth divider.124 multisynth when setting the rate of this clock output.225 * - PLL0 as clock source of multisynth 0226 * - Multisynth 0 as clock source of output divider227 * - Multisynth 0 can change PLL0233 silabs,multisynth-source = <0>;242 * - PLL1 as clock source of multisynth 1[all …]
25 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which153 description: Allow dynamic multisynth rate control
22 * enum si5351_multisynth_src - Si5351 multisynth clock source24 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO025 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N37 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)86 * @multisynth_src: multisynth source clock
107 silabs,multisynth-source = <0>;115 silabs,multisynth-source = <1>;