Home
last modified time | relevance | path

Searched full:multisynth (Results 1 – 5 of 5) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5351.yaml103 0 - use multisynth N for this output, where N is the output number
104 1 - use either multisynth 0 (if output number is 0-3) or multisynth 4
114 silabs,multisynth-source:
118 Source PLL A (0) or B (1) for the corresponding multisynth divider.
124 multisynth when setting the rate of this clock output.
225 * - PLL0 as clock source of multisynth 0
226 * - Multisynth 0 as clock source of output divider
227 * - Multisynth 0 can change PLL0
233 silabs,multisynth-source = <0>;
242 * - PLL1 as clock source of multisynth 1
[all …]
H A Dsilabs,si5341.txt13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
93 multisynth frequency dynamically.
/linux/include/linux/platform_data/
H A Dsi5351.h22 * enum si5351_multisynth_src - Si5351 multisynth clock source
24 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
25 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
37 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
86 * @multisynth_src: multisynth source clock
/linux/arch/arm/boot/dts/marvell/
H A Ddove-cubox.dts107 silabs,multisynth-source = <0>;
115 silabs,multisynth-source = <1>;
/linux/drivers/clk/
H A Dclk-si5351.c342 * Feedback Multisynth Divider Equations [2]
349 * Feedback Multisynth Register Equations
514 /* write multisynth parameters */ in si5351_pll_set_rate()
555 * Output Clock Multisynth Register Equations
771 /* write multisynth parameters */ in si5351_msynth_set_rate()
1289 if (!of_property_read_u32(child, "silabs,multisynth-source", in si5351_dt_parse()
1302 "invalid parent %d for multisynth %d\n", in si5351_dt_parse()
1508 "failed to reparent multisynth %d to %d\n", in si5351_i2c_probe()