Searched +full:mt8196 +full:- +full:apmixedsys (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o5 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg…6 obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o7 obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o8 obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o9 obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o10 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o11 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>17 #include "clk-mtk.h"18 #include "clk-pll.h"20 /* APMIXEDSYS PLL control register offsets */143 struct device_node *node = pdev->dev.of_node; in clk_mt8196_apmixed_probe()147 mcd = device_get_match_data(&pdev->dev); in clk_mt8196_apmixed_probe()149 return -EINVAL; in clk_mt8196_apmixed_probe()151 clk_data = mtk_alloc_clk_data(mcd->num_clks); in clk_mt8196_apmixed_probe()153 return -ENOMEM; in clk_mt8196_apmixed_probe()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only133 by apmixedsys, topckgen, infracfg and pericfg on the397 to PCI-E and USB.427 to PCI-E and USB.1006 tristate "Clock driver for MediaTek MT8196"1011 This driver supports MediaTek MT8196 basic clocks.1014 tristate "Clock driver for MediaTek MT8196 imp_iic_wrap"1018 This driver supports MediaTek MT8196 i2c clocks.1021 tristate "Clock driver for MediaTek MT8196 mcusys"1025 This driver supports MediaTek MT8196 mcusys clocks.[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: MediaTek System Clock Controller for MT819610 - Guangjie Song <guangjie.song@mediatek.com>11 - Laura Nao <laura.nao@collabora.com>15 PLLs -->16 dividers -->18 -->[all …]