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Searched +full:mt8195 +full:- +full:infracfg_ao (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
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H A Dmt8188.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
14 #include <dt-bindings/power/mediatek,mt8188-power.h>
15 #include <dt-bindings/reset/mt8188-resets.h>
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H A Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
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/freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,mt8195-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek System Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
22 The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmediatek,mt8195-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek System Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
22 The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dmediatek,lvts-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Balsam CHIHI <bchihi@baylibre.com>
14 a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU),
15 a Converter - Low Voltage Thermal Sensor converter (LVTS), and
21 - mediatek,mt7988-lvts-ap
22 - mediatek,mt8186-lvts
23 - mediatek,mt8188-lvts-ap
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dmt8195-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195
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