Searched +full:mt8195 +full:- +full:apusys_pll (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: MediaTek Functional Clock Controller for MT819510 - Chun-Jie Chen <chun-jie.chen@mediatek.com>14 PLLs -->15 dividers -->17 -->20 The devices except apusys_pll provide clock gate control in different IP blocks.[all …]
1 // SPDX-License-Identifier: GPL-2.0-only4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>6 #include "clk-mtk.h"7 #include "clk-pll.h"9 #include <dt-bindings/clock/mt8195-clk.h>10 #include <linux/clk-provider.h>62 struct device_node *node = pdev->dev.of_node; in clk_mt8195_apusys_pll_probe()67 return -ENOMEM; in clk_mt8195_apusys_pll_probe()91 struct device_node *node = pdev->dev.of_node; in clk_mt8195_apusys_pll_remove()99 { .compatible = "mediatek,mt8195-apusys_pll", },[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o5 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg…6 obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o7 obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o8 obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o9 obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o10 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o11 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o[all …]