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Searched +full:mt8186 +full:- +full:topckgen (Results 1 – 15 of 15) sorted by relevance

/linux/Documentation/devicetree/bindings/sound/
H A Dmt8186-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8186-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek AFE PCM controller for mt8186
10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
14 const: mediatek,mt8186-sound
25 reset-names:
36 mediatek,topckgen:
38 description: The phandle of the mediatek topckgen controller
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/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8186-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek System Clock Controller for MT8186
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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/linux/drivers/clk/mediatek/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg…
6 obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o
7 obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o
8 obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o
9 obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o
10 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
133 by apmixedsys, topckgen, infracfg and pericfg on the
397 to PCI-E and USB.
427 to PCI-E and USB.
647 tristate "Clock driver for MediaTek MT8186"
653 This driver supports MediaTek MT8186 clocks.
656 tristate "Clock driver for MediaTek MT8186 camsys"
660 This driver supports MediaTek MT8186 camsys and camsys_raw clocks.
663 tristate "Clock driver for MediaTek MT8186 imgsys"
667 This driver supports MediaTek MT8186 imgsys and imgsys2 clocks.
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H A Dclk-mt8186-topckgen.c1 // SPDX-License-Identifier: GPL-2.0-only
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
6 #include <linux/clk-provider.h>
8 #include <dt-bindings/clock/mt8186-clk.h>
10 #include "clk-mtk.h"
11 #include "clk-mux.h"
503 * top_scp is main clock in always-on co-processor.
553 * top_sspm is main clock in always-on co-processor, should not be closed
567 * top_spm and top_srck are main clocks in always-on co-processor.
692 return -ENOMEM; in clk_mt8186_reg_mfg_mux_notifier()
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/linux/Documentation/devicetree/bindings/dsp/
H A Dmediatek,mt8186-dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8186-dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek mt8186 DSP core
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 MediaTek mt8186 SoC contains a DSP core used for
14 advanced pre- and post- audio processing.
19 - mediatek,mt8186-dsp
20 - mediatek,mt8188-dsp
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/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,audsys.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugen Hristev <eugen.hristev@collabora.com>
18 - items:
19 - enum:
20 - mediatek,mt2701-audsys
21 - mediatek,mt6765-audsys
22 - mediatek,mt6779-audsys
23 - mediatek,mt7622-audsys
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/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-afe-clk.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt8186-afe-clk.c -- Mediatek 8186 afe clock ctrl
12 #include "mt8186-afe-common.h"
13 #include "mt8186-afe-clk.h"
14 #include "mt8186-audsys-clk.h"
76 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_set_audio_int_bus_parent()
79 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8186_set_audio_int_bus_parent()
80 afe_priv->clk[clk_id]); in mt8186_set_audio_int_bus_parent()
82 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8186_set_audio_int_bus_parent()
93 struct mt8186_afe_private *afe_priv = afe->platform_priv; in apll1_mux_setting()
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H A Dmt8186-afe-common.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-afe-common.h -- Mediatek 8186 audio driver definitions
14 #include "mt8186-reg.h"
15 #include "../common/mtk-base-afe.h"
119 /* SA suggest apply -0.3db to audio/speech path */
144 struct regmap *topckgen; member
/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
21 - $ref: /schemas/spi/spi-controller.yaml#
26 - enum:
27 - mediatek,mt8173-nor
28 - mediatek,mt8186-nor
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H A Dmediatek,spi-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
21 - mediatek,mt8365-spi
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/linux/Documentation/devicetree/bindings/power/
H A Dmediatek,power-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
17 IP cores belonging to a power domain should contain a 'power-domains'
22 pattern: '^power-controller(@[0-9a-f]+)?$'
26 - mediatek,mt6735-power-controller
27 - mediatek,mt6795-power-controller
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/linux/Documentation/devicetree/bindings/interconnect/
H A Dmediatek,cci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jia-Wei Chang <jia-wei.chang@mediatek.com>
11 - Johnson Wang <johnson.wang@mediatek.com>
15 MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
26 - description:
28 - description:
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/linux/Documentation/devicetree/bindings/usb/
H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
27 - mediatek,mt8186-mtu3
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H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
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