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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-mt8183.txt1 * Mediatek MT8183 Pin Controller
6 - compatible: value should be one of the following.
7 "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
8 - gpio-controller : Marks the device node as a gpio controller.
9 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
12 - gpio-ranges : gpio valid number range.
13 - reg: physical address base for gpio base registers. There are 10 GPIO
14 physical address base in mt8183.
17 - reg-names: gpio base register names. There are 10 gpio base register
18 names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4",
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H A Dmediatek,mt8183-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediate
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/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dpwm-mediatek.txt4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt6795-pwm": found on mt6795 SoC.
7 - "mediatek,mt7622-pwm": found on mt7622 SoC.
8 - "mediatek,mt7623-pwm": found on mt7623 SoC.
9 - "mediatek,mt7628-pwm": found on mt7628 SoC.
10 - "mediatek,mt7629-pwm": found on mt7629 SoC.
11 - "mediatek,mt8183-pwm": found on mt8183 SoC.
12 - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
13 - "mediatek,mt8365-pwm": found on mt8365 SoC.
[all …]
H A Dpwm-mtk-disp.txt4 - compatible: should be "mediatek,<name>-disp-pwm":
5 - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7 - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
8 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
9 - "mediatek,mt8183-disp-pwm": found on mt8183 SoC.$
10 - reg: physical base address and length of the controller's registers.
11 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
13 - clocks: phandle and clock specifier of the PWM reference clock.
14 - clock-names: must contain the following:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8183-kukui-jacuzzi-pico6.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi.dtsi"
8 #include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
12 chassis-type = "convertible";
13 compatible = "google,pico-sku2", "google,pico", "mediatek,mt8183";
15 bt_wakeup: bt-wakeup {
16 compatible = "gpio-keys";
17 pinctrl-names = "default";
18 pinctrl-0 = <&bt_pins_wakeup>;
[all …]
H A Dmt8183-kukui-jacuzzi-fennel-sku6.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi-fennel.dtsi"
8 #include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
12 chassis-type = "convertible";
13 compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";
19 compatible = "hid-over-i2c";
21 interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
22 pinctrl-names = "default";
23 pinctrl-0 = <&touchscreen_pins>;
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H A Dmt8183-kukui-jacuzzi-fennel-sku7.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi-fennel.dtsi"
8 #include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"
12 chassis-type = "convertible";
13 compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183";
19 compatible = "hid-over-i2c";
21 interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
22 pinctrl-names = "default";
23 pinctrl-0 = <&touchscreen_pins>;
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H A Dmt8183-kukui-jacuzzi-damu.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi.dtsi"
8 #include "mt8183-kukui-audi
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H A Dmt8183-kukui-jacuzzi-burnet.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi.dtsi"
8 #include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
12 chassis-type = "convertible";
13 compatible = "google,burnet", "mediatek,mt8183";
17 mediatek,dmic-mode = <1>; /* one-wire */
22 compatible = "hid-over-i2c";
24 pinctrl-names = "default";
25 pinctrl-0 = <&touchscreen_pins>;
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H A Dmt8183-kukui-jacuzzi-cozmo.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi.dtsi"
8 #include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
12 chassis-type = "laptop";
13 compatible = "google,cozmo", "mediatek,mt8183";
17 google,remote-bus = <0>;
22 compatible = "hid-over-i2c";
24 hid-descr-addr = <0x20>;
26 pinctrl-names = "default";
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H A Dmt8183-kukui-jacuzzi-fennel-sku1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi-fennel.dtsi"
8 #include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
12 chassis-type = "convertible";
13 compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183";
16 compatible = "pwm-leds";
17 keyboard_backlight: led-0 {
20 max-brightness = <1023>;
32 compatible = "hid-over-i2c";
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H A Dmt8183-pumpkin.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include "mt8183.dtsi"
15 model = "Pumpkin MT8183";
16 compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183";
28 stdout-path = "serial0:921600n8";
31 reserved-memory {
32 #address-cells = <2>;
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H A Dmt8183-evb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include "mt8183.dtsi"
13 model = "MediaTek MT8183 evaluation board";
14 chassis-type = "embedded";
15 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
27 stdout-path = "serial0:921600n8";
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
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H A Dmt8183-kukui-kodama.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui.dtsi"
8 #include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
11 ppvarn_lcd: ppvarn-lcd {
12 compatible = "regulator-fixed";
13 regulator-name = "ppvarn_lcd";
14 pinctrl-names = "default";
15 pinctrl-0 = <&ppvarn_lcd_en>;
17 enable-active-high;
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H A Dmt8183-kukui-krane.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "mt8183-kukui.dtsi"
7 #include "mt8183-kukui-audio-max98357a.dtsi"
10 ppvarn_lcd: ppvarn-lcd {
11 compatible = "regulator-fixed";
12 regulator-name = "ppvarn_lcd";
13 pinctrl-names = "default";
14 pinctrl-0 = <&ppvarn_lcd_en>;
16 enable-active-high;
21 ppvarp_lcd: ppvarp-lcd {
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H A Dmt8183-kukui-jacuzzi.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "mt8183-kukui.dtsi"
7 /* Must come after mt8183-kukui.dtsi to modify cros_ec */
8 #include <arm/cros-ec-keyboard.dtsi>
11 pp1200_mipibrdg: pp1200-mipibrdg {
12 compatible = "regulator-fixed";
13 regulator-name = "pp1200_mipibrdg";
14 pinctrl-names = "default";
15 pinctrl-0 = <&pp1200_mipibrdg_en>;
17 enable-active-high;
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H A Dmt8183-kukui-jacuzzi-juniper.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi.dtsi"
11 compatible = "hid-over-i2c";
13 hid-descr-addr = <0x20>;
15 pinctrl-names = "default";
16 pinctrl-0 = <&trackpad_pins>;
18 interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
20 wakeup-source;
25 qcom,ath10k-calibration-variant = "GO_JUNIPER";
H A Dmt8183-kukui-jacuzzi-willow.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi.dtsi"
11 compatible = "hid-over-i2c";
13 hid-descr-addr = <0x20>;
15 pinctrl-names = "default";
16 pinctrl-0 = <&trackpad_pins>;
18 interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
20 wakeup-source;
25 qcom,ath10k-calibration-variant = "GO_JUNIPER";
H A Dmt8183-kukui-jacuzzi-fennel.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi.dtsi"
10 mediatek,dmic-mode = <1>; /* one-wire */
15 compatible = "hid-over-i2c";
17 hid-descr-addr = <0x20>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&trackpad_pins>;
22 interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
24 wakeup-source;
H A Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbi
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H A Dmtk-sd.txt10 - compatible: value should be either of the following.
11 "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
12 "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
13 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
14 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
15 "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
16 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
17 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
18 "mediatek,mt7622-mmc": for MT7622 SoC
19 "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
[all …]
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dmtk-uart.txt4 - compatible should contain:
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
13 * "mediatek,mt6795-uart" for MT6795 compatible UARTS
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
21 - enum:
22 - mediatek,mt2701-dpi
23 - mediatek,mt7623-dpi
24 - mediatek,mt8173-dpi
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H A Dmediatek,dpi.txt5 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
9 - compatible: "mediatek,<chip>-dpi"
10 the supported chips are mt2701, mt7623, mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "pixel", "engine", and "pll"
16 - port: Output port node with endpoint definitions as described in
21 - pinctrl-names: Contain "default" and "sleep".
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