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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmediatek,smi-larb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controller
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H A Dmediatek,smi-larb.txt1 SMI (Smart Multimedia Interface) Local Arbiter
6 - compatible : must be one of :
7 "mediatek,mt2701-smi-larb"
8 "mediatek,mt2712-smi-larb"
9 "mediatek,mt6779-smi-larb"
10 "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
11 "mediatek,mt8167-smi-larb"
12 "mediatek,mt8173-smi-larb"
13 "mediatek,mt8183-smi-larb"
14 - reg : the register and size of this local arbiter.
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H A Dmediatek,smi-common.txt1 SMI (Smart Multimedia Interface) Common
5 Mediatek SMI have two generations of HW architecture, here is the list
8 generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
10 There's slight differences between the two SMI, for generation 2, the
11 register which control the iommu port is at each larb's register base. But
12 for generation 1, the register is at smi ao base(smi always on register
13 base). Besides that, the smi async clock should be prepared and enabled for
14 SMI generation 1 to transform the smi clock into emi clock domain, but that is
15 not needed for SMI generation 2.
18 - compatible : must be one of :
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H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SMI (Smart Multimedia Interface) Common
11 - Yong Wu <yong.wu@mediatek.com>
16 MediaTek SMI have two generations of HW architecture, here is the list
19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
21 There's slight differences between the two SMI, for generation 2, the
22 register which control the iommu port is at each larb's register base. But
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/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dmediatek,iommu.txt6 ARM Short-Descriptor translation table format for address translation.
14 +--------+
16 gals0-rx gals1-rx (Global Async Local Sync rx)
19 gals0-tx gals1-tx (Global Async Local Sync tx)
21 +--------+
23 SMI Common(Smart Multimedia Interface Common)
25 +----------------+-------
27 | gals-rx There may be GALS in some larbs.
30 | gals-tx
32 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
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H A Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
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H A Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-binding
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H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
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H A Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
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H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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H A Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
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/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsy
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H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,disp.txt29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller
38 "mediatek,<chip>-disp-gamma" - gamma correction
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dmediatek-jpeg-decoder.txt6 - compatible : must be one of the following string:
7 "mediatek,mt8173-jpgdec"
8 "mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec"
9 "mediatek,mt2701-jpgdec"
10 - reg : physical base address of the jpeg decoder registers and length of
12 - interrupts : interrupt number to the interrupt controller.
13 - clocks: device clocks, see
14 Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "jpgdec-smi" and "jpgdec".
16 - power-domains: a phandle to the power domain, see
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H A Dmediatek-jpeg-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xia Jiang <xia.jiang@mediatek.com>
12 description: |-
18 - items:
19 - enum:
20 - mediatek,mt8173-jpgdec
21 - mediatek,mt2701-jpgdec
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