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Searched +full:mt8173 +full:- +full:hdmi +full:- +full:ddc (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,hdmi-ddc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI DDC
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
19 - mediatek,mt7623-hdmi-ddc
20 - mediatek,mt8167-hdmi-ddc
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H A Dmediatek,hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI Encoder
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
20 - mediatek,mt2701-hdmi
21 - mediatek,mt7623-hdmi
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_hdmi_ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
65 static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_set_bit() argument
68 writel(readl(ddc->regs + offset) | val, ddc->regs + offset); in sif_set_bit()
71 static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_clr_bit() argument
74 writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset); in sif_clr_bit()
77 static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_bit_is_set() argument
80 return (readl(ddc->regs + offset) & val) == val; in sif_bit_is_set()
83 static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_write_mask() argument
89 tmp = readl(ddc->regs + offset); in sif_write_mask()
92 writel(tmp, ddc->regs + offset); in sif_write_mask()
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H A Dmtk_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/arm-smccc.h>
10 #include <linux/hdmi.h>
24 #include <sound/hdmi-codec.h>
190 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) in mtk_hdmi_read() argument
192 return readl(hdmi->regs + offset); in mtk_hdmi_read()
195 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) in mtk_hdmi_write() argument
197 writel(val, hdmi->regs + offset); in mtk_hdmi_write()
200 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) in mtk_hdmi_clear_bits() argument
202 void __iomem *reg = hdmi->regs + offset; in mtk_hdmi_clear_bits()
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
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H A Dmt8173-elm.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/regulator/dlg,da9211-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include "mt8173.dtsi"
25 compatible = "pwm-backlight";
27 power-supply = <&bl_fixed_reg>;
28 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
30 pinctrl-names = "default";
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