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Searched +full:mt8167 +full:- +full:larb +full:- +full:port (Results 1 – 6 of 6) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dmediatek,iommu.txt6 ARM Short-Descriptor translation table format for address translation.
14 +--------+
16 gals0-rx gals1-rx (Global Async Local Sync rx)
19 gals0-tx gals1-tx (Global Async Local Sync tx)
21 +--------+
25 +----------------+-------
27 | gals-rx There may be GALS in some larbs.
30 | gals-tx
32 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
36 +-----+-----+ +----+----+
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H A Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8167.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
17 compatible = "mediatek,mt8167";
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,disp.txt29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller
38 "mediatek,<chip>-disp-gamma" - gamma correction
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmediatek,smi-common.txt8 generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
11 register which control the iommu port is at each larb's register base. But
18 - compatible : must be one of :
19 "mediatek,mt2701-smi-common"
20 "mediatek,mt2712-smi-common"
21 "mediatek,mt6779-smi-common"
22 "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
23 "mediatek,mt8167-smi-common"
24 "mediatek,mt8173-smi-common"
25 "mediatek,mt8183-smi-common"
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H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
22 register which control the iommu port is at each larb's register base. But
31 - enum:
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
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