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Searched +full:msm8660 +full:- +full:ebi2 (Results 1 – 5 of 5) sorted by relevance

/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ebi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm External Bus Interface 2 (EBI2)
10 The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
11 external memory (such as NAND or other memory-mapped peripherals) whereas
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,msm8660-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8660-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM8660 TLMM pin controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 Top Level Mode Multiplexer pin controller in Qualcomm MSM8660 SoC.
18 const: qcom,msm8660-pinctrl
26 gpio-reserved-ranges:
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/linux/drivers/pinctrl/qcom/
H A Dpinctrl-msm8660.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "pinctrl-msm.h"
425 .mux_bit = -1, \
428 .oe_bit = -1, \
429 .in_bit = -1, \
430 .out_bit = -1, \
431 .intr_enable_bit = -1, \
432 .intr_status_bit = -1, \
433 .intr_target_bit = -1, \
434 .intr_target_kpss_val = -1, \
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/linux/drivers/bus/
H A Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm External Bus Interface 2 (EBI2) driver
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
74 * Bits 31-28: ?
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8060-dragonboard.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/leds/common.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
7 #include "qcom-msm8660.dtsi"
12 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";
19 stdout-path = "serial0:115200n8";
23 vph: regulator-fixed {
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