Searched +full:msm +full:- +full:uartdm (Results 1 – 13 of 13) sorted by relevance
/linux/Documentation/devicetree/bindings/serial/ |
H A D | qcom,msm-uartdm.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm MSM Serial UARTDM 10 - Andy Gross <agross@kernel.org> 11 - Bjorn Andersson <bjorn.andersson@linaro.org> 12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 15 The MSM serial UARTDM hardware is designed for high-speed use cases where the 16 transmit and/or receive channels can be offloaded to a dma-engine. From a [all …]
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H A D | qcom,msm-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/serial/qcom,msm-uart.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm MSM SoC Serial UART 10 - Bjorn Andersson <andersson@kernel.org> 11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 14 The MSM serial UART hardware is designed for low-speed use cases where a 15 dma-engine isn't needed. From a software perspective it's mostly compatible 16 with the MSM serial UARTDM except that it only supports reading and writing [all …]
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/linux/arch/arm/boot/dts/qcom/ |
H A D | qcom-msm8660.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/interrupt-controller/irq.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/clock/qcom,gcc-msm8660.h> 7 #include <dt-bindings/soc/qcom,gsbi.h> 10 #address-cells = <1>; 11 #size-cells = <1>; 14 interrupt-parent = <&intc>; 17 #address-cells = <1>; [all …]
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H A D | qcom-mdm9615.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h> 13 #include <dt-bindings/clock/qcom,lcc-msm8960.h> 14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h> 15 #include <dt-bindings/mfd/qcom-rpm.h> 16 #include <dt-bindings/soc/qcom,gsbi.h> 19 #address-cells = <1>; 20 #size-cells = <1>; [all …]
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H A D | qcom-ipq4019.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 6 /dts-v1/; 8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 13 #address-cells = <1>; 14 #size-cells = <1>; 18 interrupt-parent = <&intc>; 20 reserved-memory { 21 #address-cells = <0x1>; [all …]
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H A D | qcom-msm8960.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/clock/qcom,gcc-msm8960.h> 6 #include <dt-bindings/reset/qcom,gcc-msm8960.h> 7 #include <dt-bindings/clock/qcom,lcc-msm8960.h> 8 #include <dt-bindings/mfd/qcom-rpm.h> 9 #include <dt-bindings/soc/qcom,gsbi.h> 12 #address-cells = <1>; 13 #size-cells = <1>; [all …]
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H A D | qcom-sdx55.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 9 #include <dt-bindings/clock/qcom,gcc-sdx55.h> 10 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/interconnect/qcom,sdx55.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/power/qcom-rpmpd.h> 15 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 18 #address-cells = <1>; 19 #size-cells = <1>; [all …]
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H A D | qcom-sdx65.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 9 #include <dt-bindings/clock/qcom,gcc-sdx65.h> 10 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 #include <dt-bindings/interconnect/qcom,sdx65.h> 18 #address-cells = <1>; 19 #size-cells = <1>; [all …]
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/linux/Documentation/devicetree/bindings/soc/qcom/ |
H A D | qcom,gsbi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andy Gross <agross@kernel.org> 11 - Bjorn Andersson <bjorn.andersson@linaro.org> 12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 16 representing a serial sub-node device that is mux'd as part of the GSBI 26 const: qcom,gsbi-v1.0.0 28 '#address-cells': 31 cell-index: [all …]
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | ipq8074.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h> 10 #address-cells = <2>; 11 #size-cells = <2>; 15 interrupt-parent = <&intc>; 19 compatible = "fixed-clock"; 20 clock-frequency = <32768>; 21 #clock-cells = <0>; 25 compatible = "fixed-clock"; [all …]
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H A D | ipq5332.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 8 #include <dt-bindings/clock/qcom,apss-ipq.h> 9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h> 10 #include <dt-bindings/interconnect/qcom,ipq5332.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 19 sleep_clk: sleep-clk { [all …]
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H A D | ipq5018.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 8 #include <dt-bindings/clock/qcom,apss-ipq.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/clock/qcom,gcc-ipq5018.h> 11 #include <dt-bindings/reset/qcom,gcc-ipq5018.h> 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; [all …]
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/linux/arch/arm/ |
H A D | Kconfig.debug | 1 # SPDX-License-Identifier: GPL-2.0 44 once the kernel has booted up - it's a one time check. 104 1 - undefined instruction events 105 2 - system calls 106 4 - invalid data aborts 107 8 - SIGSEGV faults 108 16 - SIGBUS faults 112 bool "Kernel low-level debugging functions (read help!)" 125 prompt "Kernel low-level debugging port" 129 bool "Kernel low-level debugging messages via Alpine UART0" [all …]
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