/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
H A D | msi-pic.txt | 1 * Freescale MSI interrupt controller 4 - compatible : compatible list, may contain one or two entries 5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, 6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or 7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic 8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is 9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3" 13 - reg : It may contain one or two regions. The first region should contain 17 region must be added because different MSI group has different MSIIR1 offset. 19 - interrupts : each one of the interrupts here is one entry per 32 MSIs, [all …]
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/linux/arch/powerpc/sysdev/ |
H A D | msi_bitmap.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright 2006-2008, Michael Ellerman, IBM Corporation. 20 spin_lock_irqsave(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs() 22 offset = bitmap_find_next_zero_area(bmp->bitmap, bmp->irq_count, 0, in msi_bitmap_alloc_hwirqs() 23 num, (1 << order) - 1); in msi_bitmap_alloc_hwirqs() 24 if (offset > bmp->irq_count) in msi_bitmap_alloc_hwirqs() 27 bitmap_set(bmp->bitmap, offset, num); in msi_bitmap_alloc_hwirqs() 28 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs() 34 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs() 35 return -ENOMEM; in msi_bitmap_alloc_hwirqs() [all …]
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/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | msi-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MSI controller 10 - Marc Zyngier <maz@kernel.org> 13 An MSI controller signals interrupts to a CPU when a write is made 14 to an MMIO address by some master. An MSI controller may feature a 18 "#msi-cells": 20 The number of cells in an msi-specifier, required if not zero. [all …]
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H A D | marvell,gicp.txt | 2 ----------------------- 11 - compatible: Must be "marvell,ap806-gicp" 13 - reg: Must be the address and size of the GICP SPI registers 15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available 18 - msi-controller: indicates that this is an MSI controller 22 gicp_spi: gicp-spi@3f0040 { 23 compatible = "marvell,ap806-gicp"; 25 marvell,spi-ranges = <64 64>, <288 64>; 26 msi-controller;
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H A D | ti,sci-inta.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lokesh Vutla <lokeshvutla@ti.com> 13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# 22 +-----------------------------------------+ 24 | +--------------+ +------------+ | 25 m ------>| | vint | bit | | 0 |.....|63| vint0 | 26 . | +--------------+ +------------+ | +------+ [all …]
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H A D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marc Zyngier <marc.zyngier@arm.com> 22 - $ref: /schemas/interrupt-controller.yaml# 27 - items: 28 - enum: 29 - arm,arm11mp-gic 30 - arm,cortex-a15-gic [all …]
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/linux/Documentation/devicetree/bindings/bus/ |
H A D | xlnx,versal-net-cdx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 15 on run-time. 18 and a unique device ID (for MSI) corresponding to a requestor ID 20 are used to configure SMMU and GIC-ITS respectively. 22 iommu-map property is used to define the set of stream ids 25 The MSI writes are accompanied by sideband data (Device ID). 26 The msi-map property is used to associate the devices with the [all …]
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/linux/Documentation/devicetree/bindings/pci/ |
H A D | aardvark-pci.txt | 8 - compatible: Should be "marvell,armada-3700-pcie" 9 - reg: range of registers for the PCIe controller 10 - interrupts: the interrupt line of the PCIe controller 11 - #address-cells: set to <3> 12 - #size-cells: set to <2> 13 - device_type: set to "pci" 14 - ranges: ranges for the PCI memory and I/O regions 15 - #interrupt-cells: set to <1> 16 - msi-controller: indicates that the PCIe controller can itself 17 handle MSI interrupts [all …]
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H A D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller 5 - compatible: should be "apm,xgene1-msi" to identify 6 X-Gene v1 PCIe MSI controller block. 7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node 8 - reg: physical base address (0x79000000) and length (0x900000) for controller 9 registers. These registers include the MSI termination address and data 10 registers as well as the MSI interrupt status registers. 11 - reg-names: not required 12 - interrupts: A list of 16 interrupt outputs of the controller, starting from 14 - interrupt-names: not required [all …]
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H A D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be: 5 - "nvidia,tegra20-pcie": for Tegra20 6 - "nvidia,tegra30-pcie": for Tegra30 7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132 8 - "nvidia,tegra210-pcie": for Tegra210 9 - "nvidia,tegra186-pcie": for Tegra186 10 - power-domains: To ungate power partition by BPMP powergate driver. Must 13 - device_type: Must be "pci" 14 - reg: A list of physical base address and length for each set of controller 15 registers. Must contain an entry for each entry in the reg-names property. [all …]
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H A D | xilinx-versal-cpm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> 13 - $ref: /schemas/pci/pci-host-bridge.yaml# 18 - xlnx,versal-cpm-host-1.00 19 - xlnx,versal-cpm5-host 23 - description: CPM system level control and status registers. 24 - description: Configuration space region and bridge registers. [all …]
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H A D | microchip,pcie-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 - $ref: plda,xpressrich3-axi-common.yaml# 14 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 18 const: microchip,pcie-host-1.0 # PolarFire 32 - description: FIC0's clock 33 - description: FIC1's clock [all …]
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/linux/arch/powerpc/boot/dts/fsl/ |
H A D | qoriq-mpic.dtsi | 36 interrupt-controller; 37 #address-cells = <0>; 38 #interrupt-cells = <4>; 40 compatible = "fsl,mpic", "chrp,open-pic"; 41 device_type = "open-pic"; 42 clock-frequency = <0x0>; 46 compatible = "fsl,mpic-global-timer"; 54 msi0: msi@41600 { 55 compatible = "fsl,mpic-msi"; 57 msi-available-ranges = <0 0x100>; [all …]
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/linux/arch/arm64/boot/dts/marvell/ |
H A D | armada-ap80x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/thermal/thermal.h> 11 /dts-v1/; 14 #address-cells = <2>; 15 #size-cells = <2>; 25 compatible = "arm,psci-0.2"; 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; [all …]
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H A D | armada-ap810-ap0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 /dts-v1/; 14 compatible = "marvell,armada-ap810"; 15 #address-cells = <2>; 16 #size-cells = <2>; 24 compatible = "arm,psci-0.2"; 28 ap810-ap0 { 29 #address-cells = <2>; 30 #size-cells = <2>; [all …]
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/linux/Documentation/devicetree/bindings/misc/ |
H A D | fsl,qoriq-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Li <Frank.Li@nxp.com> 13 The Freescale Management Complex (fsl-mc) is a hardware resource 15 network-oriented packet processing applications. After the fsl-mc 22 For an overview of the DPAA2 architecture and fsl-mc bus see: 26 same hardware "isolation context" and a 10-bit value called an ICID 31 between ICIDs and IOMMUs, so an iommu-map property is used to define [all …]
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/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm-hr2.dtsi | 33 #include <dt-bindings/interrupt-controller/arm-gic.h> 34 #include <dt-bindings/interrupt-controller/irq.h> 39 interrupt-parent = <&gic>; 40 #address-cells = <1>; 41 #size-cells = <1>; 44 #address-cells = <1>; 45 #size-cells = <0>; 49 compatible = "arm,cortex-a9"; 50 next-level-cache = <&L2>; 56 compatible = "arm,cortex-a9-pmu"; [all …]
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H A D | bcm-nsp.dtsi | 33 #include <dt-bindings/interrupt-controller/arm-gic.h> 34 #include <dt-bindings/interrupt-controller/irq.h> 35 #include <dt-bindings/clock/bcm-nsp.h> 38 #address-cells = <1>; 39 #size-cells = <1>; 42 interrupt-parent = <&gic>; 53 #address-cells = <1>; 54 #size-cells = <0>; 58 compatible = "arm,cortex-a9"; 59 next-level-cache = <&L2>; [all …]
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/linux/arch/arm64/boot/dts/broadcom/northstar2/ |
H A D | ns2.dtsi | 35 #include <dt-bindings/interrupt-controller/arm-gic.h> 36 #include <dt-bindings/clock/bcm-ns2.h> 40 interrupt-parent = <&gic>; 41 #address-cells = <2>; 42 #size-cells = <2>; 45 #address-cells = <2>; 46 #size-cells = <0>; 50 compatible = "arm,cortex-a57"; 52 enable-method = "psci"; 53 next-level-cache = <&CLUSTER0_L2>; [all …]
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/linux/arch/arm64/boot/dts/apm/ |
H A D | apm-shadowcat.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC 9 compatible = "apm,xgene-shadowcat"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 15 #address-cells = <2>; 16 #size-cells = <0>; 22 enable-method = "spin-table"; 23 cpu-release-addr = <0x1 0x0000fff8>; [all …]
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/linux/arch/arm64/boot/dts/cavium/ |
H A D | thunder2-99xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 * Copyright (c) 2013-2016 Broadcom 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 21 #address-cells = <0x2>; 22 #size-cells = <0x0>; 28 enable-method = "psci"; [all …]
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/linux/arch/arm64/boot/dts/freescale/ |
H A D | fsl-ls1043a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/gpio/gpio.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; [all …]
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H A D | fsl-ls1046a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/gpio/gpio.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 37 #address-cells = <1>; [all …]
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/linux/arch/powerpc/sysdev/xics/ |
H A D | ics-native.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 20 #include <linux/msi.h> 42 return in->base + 0x800 + ((vec - in->ibase) << 2); in ics_native_xive() 52 pr_devel("ics-native: unmask virq %d [hw 0x%x]\n", d->irq, vec); in ics_native_unmask_irq() 54 if (vec < in->ibase || vec >= (in->ibase + in->icount)) in ics_native_unmask_irq() 57 server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0); in ics_native_unmask_irq() 65 * The generic MSI code returns with the interrupt disabled on the in ics_native_startup() 66 * card, using the MSI mask bits. Firmware doesn't appear to unmask in ics_native_startup() 89 pr_devel("ics-native: mask virq %d [hw 0x%x]\n", d->irq, vec); in ics_native_mask_irq() 91 if (vec < in->ibase || vec >= (in->ibase + in->icount)) in ics_native_mask_irq() [all …]
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/linux/arch/powerpc/boot/dts/ |
H A D | akebono.dts | 12 /dts-v1/; 17 #address-cells = <2>; 18 #size-cells = <2>; 21 dcr-parent = <&{/cpus/cpu@0}>; 28 #address-cells = <1>; 29 #size-cells = <0>; 35 clock-frequency = <1600000000>; // 1.6 GHz 36 timebase-frequency = <100000000>; // 100Mhz 37 i-cache-line-size = <32>; 38 d-cache-line-size = <32>; [all …]
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