Home
last modified time | relevance | path

Searched +full:msi +full:- +full:offset (Results 1 – 25 of 395) sorted by relevance

12345678910>>...16

/linux/arch/powerpc/sysdev/
H A Dfsl_msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
11 #include <linux/msi.h>
24 #include <asm/ppc-pci.h>
39 #define msi_hwirq(msi, msir_index, intr_index) \ argument
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
47 u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
63 * in the cascade interrupt. So, this MSI interrupt has been acked
71 struct fsl_msi *msi_data = irqd->domain->host_data; in fsl_msi_print_chip()
[all …]
/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
45 | +-------------+ +-------------+ |
46 +---------------------------------------------------------------------+
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
[all …]
/linux/drivers/irqchip/
H A Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
29 #include <linux/irqchip/irq-msi-lib.h>
34 * [25:16] lowest SPI assigned to MSI
36 * [9:0] Numer of SPIs assigned to MSI
52 /* APM X-Gene with GICv2m MSI_IIDR register value */
72 u32 spi_offset; /* offset to be subtracted from SPI number */
[all …]
/linux/drivers/xen/xen-pciback/
H A Dconf_space_capability.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Backend - Handles the virtual fields found on the capability lists
26 .offset = PCI_CAP_LIST_ID,
36 list_add_tail(&cap->cap_list, &capabilities); in register_capability()
46 cap_offset = pci_find_capability(dev, cap->capability); in xen_pcibk_config_capability_add_fields()
48 dev_dbg(&dev->dev, "Found capability 0x%x at 0x%x\n", in xen_pcibk_config_capability_add_fields()
49 cap->capability, cap_offset); in xen_pcibk_config_capability_add_fields()
57 cap->fields, in xen_pcibk_config_capability_add_fields()
68 static int vpd_address_write(struct pci_dev *dev, int offset, u16 value, in vpd_address_write() argument
75 return pci_write_config_word(dev, offset, value); in vpd_address_write()
[all …]
/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #include <linux/msi.h>
29 #define PAB_REG_ADDR(offset, win) \ argument
30 (offset + (win * PAB_REG_BLOCK_SIZE))
31 #define PAB_EXT_REG_ADDR(offset, win) \ argument
32 (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
100 /* starting offset of INTX bits in status register */
103 /* supported number of MSI interrupts */
106 /* MSI registers */
136 struct mobiveil_msi { /* MSI information */
[all …]
/linux/include/linux/
H A Dpci-epc.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pci-epf.h>
17 UNKNOWN_INTERFACE = -1,
36 * struct pci_epc_map - information about EPC memory for mapping a RC PCI
65 * struct pci_epc_ops - set of function pointers for performing EPC operations
69 * @align_addr: operation to get the mapping address, mapping size and offset
74 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
76 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
77 * the MSI capability register
78 * @set_msix: ops to set the requested number of MSI-X interrupts in the
[all …]
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_lib.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
9 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV
12 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It
20 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_cache_ring_dcb_sriov()
22 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; in ixgbe_cache_ring_dcb_sriov()
25 u8 tcs = adapter->hw_tc in ixgbe_cache_ring_dcb_sriov()
153 int tc, offset, rss_i, i; ixgbe_cache_ring_dcb() local
[all...]
/linux/drivers/pci/controller/
H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
26 #include <linux/irqchip/irq-msi-lib.h>
31 #include <linux/msi.h>
258 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
346 struct tegra_msi msi; member
358 static inline struct tegra_pcie *msi_to_pcie(struct tegra_msi *msi) in msi_to_pcie() argument
360 return container_of(msi, struct tegra_pcie, msi); in msi_to_pcie()
378 unsigned long offset) in afi_writel() argument
[all …]
H A Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
18 #include <linux/pci-epc.h>
20 #include <linux/pci-epf.h>
24 #include "pcie-rockchip.h"
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
33 * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ
36 * the sending of a memory write (MSI) / normal message (INTX
38 * @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ
[all …]
H A Dvmd.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/irqchip/irq-msi-lib.h>
13 #include <linux/msi.h>
15 #include <linux/pci-acpi.h>
16 #include <linux/pci-ecam.h>
56 * vendor-specific capability space
61 * Device may use MSI-X vector 0 for software triggering and will not
62 * be used for MSI remapping
67 * Device can bypass remapping MSI-X transactions into its MSI-X table,
68 * avoiding the requirement of a VMD MSI domain for child device
[all …]
/linux/Documentation/misc-devices/
H A Dspear-pcie-gadget.rst1 .. SPDX-License-Identifier: GPL-2.0
37 -----------------------
42 no_of_msi zero if MSI is not enabled by host. A positive value is the
43 number of MSI vector granted.
48 bar0_rw_offset returns offset of bar0 for which bar0_data will return value.
53 ------------------------
58 INTA, MSI or NO_INT). Select MSI only when you have programmed
60 no_of_msi number of MSI vector needed.
61 inta write 1 to assert INTA and 0 to de-assert.
62 send_msi write MSI vector to be sent.
[all …]
/linux/drivers/net/wireless/ath/ath11k/
H A Dpci.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
8 #include <linux/msi.h>
49 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); in ath11k_pci_bus_wake_up()
56 mhi_device_put(ab_pci->mhi_ctr in ath11k_pci_bus_release()
59 ath11k_pci_get_window_start(struct ath11k_base * ab,u32 offset) ath11k_pci_get_window_start() argument
75 ath11k_pci_select_window(struct ath11k_pci * ab_pci,u32 offset) ath11k_pci_select_window() argument
92 ath11k_pci_window_write32(struct ath11k_base * ab,u32 offset,u32 value) ath11k_pci_window_write32() argument
111 ath11k_pci_window_read32(struct ath11k_base * ab,u32 offset) ath11k_pci_window_read32() argument
237 ath11k_pci_set_link_reg(struct ath11k_base * ab,u32 offset,u32 value,u32 mask) ath11k_pci_set_link_reg() argument
[all...]
H A Dpcic.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
15 "mhi-er0",
16 "mhi-er1",
29 "host2wbm-desc-feed",
30 "host2reo-re-injection",
31 "host2reo-command",
32 "host2rxdma-monitor-ring3",
33 "host2rxdma-monitor-ring2",
[all …]
/linux/drivers/pci/controller/plda/
H A Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
18 #include <linux/msi.h>
21 #include <linux/pci-ecam.h>
26 #include "../pci-host-common.h"
27 #include "pcie-plda.h"
88 /* PCIe Config space MSI capability structure */
136 .offset = PCIE_EVENT_INT, \
143 .offset = SEC_ERROR_INT, \
150 .offset = DED_ERROR_INT, \
[all …]
/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dhsta.txt10 Currently only the MSI support is used by Linux using the following
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
18 register offset of 0x00, the second to 0x10, etc.
/linux/drivers/iommu/iommufd/
H A Ddriver.c1 // SPDX-License-Identifier: GPL-2.0-only
6 /* Driver should use a per-structure helper in include/linux/iommufd.h */
12 return -EINVAL; in _iommufd_object_depend()
14 if (obj_dependent->type != obj_depended->type) in _iommufd_object_depend()
15 return -EINVAL; in _iommufd_object_depend()
17 refcount_inc(&obj_depended->users); in _iommufd_object_depend()
22 /* Driver should use a per-structure helper in include/linux/iommufd.h */
27 obj_dependent->type != obj_depended->type)) in _iommufd_object_undepend()
30 refcount_dec(&obj_depended->users); in _iommufd_object_undepend()
35 * Allocate an @offset to return to user space to use for an mmap() syscall
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,mpic-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
11 -------------------------------------------
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
39 this. The address specified in the msi-address-64 property is the PCI
[all …]
/linux/arch/um/drivers/
H A Dvirt-pci.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/irqchip/irq-msi-lib.h>
12 #include <linux/msi.h>
16 #include "virt-pci.h"
35 static unsigned long um_pci_cfgspace_read(void *priv, unsigned int offset, in um_pci_cfgspace_read() argument
39 struct um_pci_device *dev = reg->dev; in um_pci_cfgspace_read()
57 return dev->ops->cfgspace_read(dev, offset, size); in um_pci_cfgspace_read()
60 static void um_pci_cfgspace_write(void *priv, unsigned int offset, int size, in um_pci_cfgspace_write() argument
64 struct um_pci_device *dev = reg->dev; in um_pci_cfgspace_write()
82 dev->ops->cfgspace_write(dev, offset, size, val); in um_pci_cfgspace_write()
[all …]
/linux/drivers/pci/endpoint/
H A Dpci-epc-core.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pci-epc.h>
14 #include <linux/pci-epf.h>
15 #include <linux/pci-ep-cfs.h>
29 * pci_epc_put() - release the PCI endpoint controller
39 module_put(epc->ops->owner); in pci_epc_put()
40 put_device(&epc->dev); in pci_epc_put()
45 * pci_epc_get() - get the PCI endpoint controller
53 int ret = -EINVAL; in pci_epc_get()
62 if (try_module_get(epc->ops->owner)) in pci_epc_get()
[all …]
/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net_ctrl.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
17 /* 64-bit per app capabilities */
23 * THB-350, 32k needs to be reserved.
27 /* Offset in Freelist buffer where packet starts on RX */
61 /* Hash type pre-pended when a RSS hash was computed */
80 /* Read/Write config words (0x0000 - 0x002c)
87 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions
88 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes
92 * - define Error details in UPDATE
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-mpic.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
40 compatible = "fsl,mpic", "chrp,open-pic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
46 compatible = "fsl,mpic-global-timer";
54 msi0: msi@41600 {
55 compatible = "fsl,mpic-msi";
[all …]
/linux/drivers/scsi/csiostor/
H A Dcsio_hw_t5.c4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
42 * Truncation intentional: we only read the bottom 32-bits of the in csio_t5_set_mem_win()
43 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to in csio_t5_set_mem_win()
46 * accesses to our Configuration Space and we need to set up the PCI-E in csio_t5_set_mem_win()
48 * coming across the PCI-E link. in csio_t5_set_mem_win()
51 /* For T5, only relative offset inside the PCIe BAR is passed */ in csio_t5_set_mem_win()
60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10), in csio_t5_set_mem_win()
76 -1, 1 }, in csio_t5_pcie_intr_handler()
[all …]

12345678910>>...16