| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | fsl,mpic-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
11 -------------------------------------------
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
39 this. The address specified in the msi-address-64 property is the PCI
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| H A D | marvell,ap806-gicp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-gicp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
20 const: marvell,ap806-gicp
25 marvell,spi-ranges:
26 description: Tuples of GIC SPI interrupt ranges available for this GICP
27 $ref: /schemas/types.yaml#/definitions/uint32-matrix
30 - description: SPI interrupt base
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| H A D | marvell,gicp.txt | 2 -----------------------
11 - compatible: Must be "marvell,ap806-gicp"
13 - reg: Must be the address and size of the GICP SPI registers
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
18 - msi-controller: indicates that this is an MSI controller
22 gicp_spi: gicp-spi@3f0040 {
23 compatible = "marvell,ap806-gicp";
25 marvell,spi-ranges = <64 64>, <288 64>;
26 msi-controller;
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| H A D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | msi-pic.txt | 1 * Freescale MSI interrupt controller
4 - compatible : compatible list, may contain one or two entries
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
13 - reg : It may contain one or two regions. The first region should contain
17 region must be added because different MSI group has different MSIIR1 offset.
19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
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| /freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | qoriq-mpic.dtsi | 36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
40 compatible = "fsl,mpic", "chrp,open-pic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
46 compatible = "fsl,mpic-global-timer";
54 msi0: msi@41600 {
55 compatible = "fsl,mpic-msi";
57 msi-available-ranges = <0 0x100>;
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| H A D | mpc8572ds_camp_core0.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
10 * Copyright 2007-2009 Freescale Semiconductor Inc.
17 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
38 gpio-controller@f000 {
40 l2-cache-controller@20000 {
41 cache-size = <0x80000>; // L2, 512K
56 protected-sources = <
59 0xe4 0xe5 0xe6 0xe7 /* msi */
63 msi@41600 {
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| H A D | mpc8572ds_camp_core1.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
9 * Please note to add "-b 1" for core1's dts compiling.
11 * Copyright 2007-2009 Freescale Semiconductor Inc.
18 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
33 ecm-law@0 {
39 memory-controller@2000 {
42 memory-controller@6000 {
54 gpio-controller@f000 {
57 l2-cache-controller@20000 {
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| H A D | pq3-mpic.dtsi | 36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
41 device_type = "open-pic";
42 big-endian;
43 single-cpu-affinity;
44 last-interrupt-source = <255>;
48 compatible = "fsl,mpic-global-timer";
57 compatible = "fsl,mpic-v3.1-msgr";
66 msi@41600 {
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| /freebsd/sys/contrib/device-tree/Bindings/misc/ |
| H A D | fsl,qoriq-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
16 block is enabled, pools of hardware resources are available, such as
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
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| H A D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
6 block is enabled, pools of hardware resources are available, such as
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
35 For generic MSI bindings, see
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| /freebsd/sys/contrib/device-tree/src/arm64/amazon/ |
| H A D | alpine-v2.dtsi | 4 * Antoine Tenart <antoine.tenart@free-electrons.com>
6 * This software is available to you under a choice of one of two
8 * General Public License (GPL) Version 2, available from the file
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 interrupt-parent = <&gic>;
43 #address-cells = <2>;
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| /freebsd/sys/contrib/device-tree/src/arm64/al/ |
| H A D | alpine-v2.dtsi | 4 * Antoine Tenart <antoine.tenart@free-electrons.com>
6 * This software is available to you under a choice of one of two
8 * General Public License (GPL) Version 2, available from the file
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | layerscape-pci.txt | 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
9 Also as per the available Reference Manuals, there is no specific 'version'
10 register available in the Freescale PCIe controller register set,
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
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| H A D | nvidia,tegra194-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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| H A D | nvidia,tegra194-pcie.txt | 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
5 snps,dw-pcie-ep.yaml.
10 - power-domains: A phandle to the node that controls power to the respective
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
26 "config": As per the definition in snps,dw-pcie.yaml
28 Translation Unit) registers of the PCIe core are made available
31 available
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| H A D | fsl,layerscape-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
16 which is used to describe the PLL settings at the time of chip-reset.
18 Also as per the available Reference Manuals, there is no specific 'version'
19 register available in the Freescale PCIe controller register set,
26 - enum:
27 - fsl,ls1012a-pcie
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| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| /freebsd/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2838_pci.c | 1 /*-
2 * SPDX-License-Identifier: ISC
22 * BCM2838-compatible PCI-express controller.
94 * (although at time of writing the largest memory size available for purchase
96 * limited portion of the address space. Worse, the PCI-e controller has further
108 #define REG_VALUE_DMA_WINDOW_LOW (MAX_MEMORY_LOG2 - 0xf)
112 (((MAX_MEMORY_LOG2 - 0xf) << 0x1b) | DMA_WINDOW_ENABLE)
135 {"brcm,bcm2711-pcie", 1},
136 {"brcm,bcm7211-pcie", 1},
137 {"brcm,bcm7445-pcie", 1},
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| /freebsd/sys/contrib/device-tree/src/powerpc/ |
| H A D | mpc8308rdb.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <16384>;
34 i-cache-size = <16384>;
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| H A D | mpc8308_p1m.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <16384>;
33 i-cache-size = <16384>;
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| H A D | mpc8610_hpcd.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <32768>; // L1
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ti/ |
| H A D | k3-bcdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-bcdma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
16 mode channels of K3 UDMA-P.
23 Split channels can be used to service PSI-L based peripherals.
24 The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
25 with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
34 - ti,am62a-dmss-bcdma-csirx
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| /freebsd/sys/contrib/device-tree/src/arm64/amd/ |
| H A D | amd-seattle-soc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
10 interrupt-parent = <&gic0>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 /include/ "amd-seattle-clks.dtsi"
16 gic0: interrupt-controller@e1101000 {
17 compatible = "arm,gic-400", "arm,cortex-a15-gic";
18 interrupt-controller;
19 #interrupt-cells = <3>;
20 #address-cells = <2>;
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| /freebsd/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | riscv,iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <tjeznach@rivosinc.com>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
16 the PCIe specification, two stage address translation and MSI remapping.
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
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