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Searched +full:mram +full:- +full:cfg (Results 1 – 14 of 14) sorted by relevance

/linux/Documentation/devicetree/bindings/net/can/
H A Dbosch,m_can.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Chandrasekar Ramakrishnan <rcsekar@samsung.com>
15 - $ref: can-controller.yaml#
23 - description: M_CAN registers map
24 - description: message RAM
26 reg-names:
28 - const: m_can
29 - const: message_ram
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp153.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
12 compatible = "arm,cortex-a7";
13 clock-frequency = <650000000>;
19 arm-pmu {
22 interrupt-affinity = <&cpu0>, <&cpu1>;
37 reg-names = "m_can", "message_ram";
40 interrupt-names = "int0", "int1";
42 clock-names = "hclk", "cclk";
43 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
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H A Dstm32mp133.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
14 reg-names = "m_can", "message_ram";
17 interrupt-names = "int0", "int1";
19 clock-names = "hclk", "cclk";
20 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
27 reg-names = "m_can", "message_ram";
30 interrupt-names = "int0", "int1";
32 clock-names = "hclk", "cclk";
33 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
19 compatible = "ti,j721e-esm";
21 bootph-pre-ram;
23 ti,esm-pins = <0>, <1>, <2>, <85>;
32 compatible = "ti,am654-timer";
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H A Dk3-am62-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 bootph-all;
11 compatible = "pinctrl-single";
13 #pinctrl-cells = <1>;
14 pinctrl-single,register-width = <32>;
15 pinctrl-single,function-mask = <0xffffffff>;
19 bootph-pre-ram;
20 compatible = "ti,j721e-esm";
23 ti,esm-pins = <0>, <1>, <2>, <85>;
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H A Dk3-am62p-j722s-common-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
15 pinctrl-single,gpio-range =
19 bootph-all;
21 mcu_pmx_range: gpio-range {
22 #pinctrl-single,gpio-range-cells = <3>;
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H A Dk3-am65-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "simple-bus";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 cpsw_mac_syscon: ethernet-mac-syscon@200 {
16 compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
21 compatible = "ti,am654-phy-gmii-sel";
23 #phy-cells = <1>;
29 compatible = "pinctrl-single";
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H A Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-j721s2-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/dma/at91.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/mfd/at91-usart.h>
19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
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H A Dlan966x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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/linux/arch/arm/boot/dts/ti/omap/
H A Ddra76x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
12 target-module@42c01900 {
13 compatible = "ti,sysc-dra7-mcan", "ti,sysc";
15 #address-cells = <1>;
16 #size-cells = <1>;
20 reg-names = "rev", "sysc", "syss";
21 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
23 ti,syss-mask = <1>;
25 clock-names = "fck";
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/linux/arch/arm64/boot/dts/tesla/
H A Dfsd.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
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/linux/drivers/net/can/m_can/
H A Dm_can.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
8 * https://github.com/linux-can/can-doc/tree/master/m_can
332 return cdev->ops->read_reg(cdev, reg); in m_can_read()
338 cdev->ops->write_reg(cdev, reg, val); in m_can_write()
345 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + in m_can_fifo_read()
351 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count); in m_can_fifo_read()
358 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + in m_can_fifo_write()
364 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count); in m_can_fifo_write()
370 return cdev->ops->write_fifo(cdev, fpi, &val, 1); in m_can_fifo_write_no_off()
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