Searched +full:mpfs +full:- +full:clkcfg (Results 1 – 11 of 11) sorted by relevance
/freebsd/sys/contrib/device-tree/src/riscv/microchip/ |
H A D | mpfs.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 8 #address-cells = <2>; 9 #size-cells = <2>; 11 compatible = "microchip,mpfs"; 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <1000000>; [all …]
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H A D | microchip-mpfs.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 6 #include "microchip-mpfs-fabric.dtsi" 9 #address-cells = <2>; 10 #size-cells = <2>; 12 compatible = "microchip,mpfs"; 15 #address-cells = <1>; 16 #size-cells = <0>; [all …]
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H A D | microchip-mpfs-icicle-kit.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 6 #include "microchip-mpfs.dtsi" 12 model = "Microchip PolarFire-SoC Icicle Kit"; 13 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; 25 stdout-path = "serial1:115200n8"; 29 timebase-frequency = <RTCCLK_FREQ>; 35 clocks = <&clkcfg CLK_DDRC>; 42 clocks = <&clkcfg CLK_DDRC>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | microchip,mpfs-clkcfg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller, 17 user nodes by the CLKCFG node phandle and the clock index in the group, from 22 const: microchip,mpfs-clkcfg 26 - description: | 31 - description: | [all …]
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H A D | microchip,mpfs.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller, 17 user nodes by the CLKCFG node phandle and the clock index in the group, from 22 const: microchip,mpfs-clkcfg 26 - description: | 31 - description: | [all …]
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/freebsd/sys/contrib/device-tree/Bindings/net/can/ |
H A D | microchip,mpfs-can.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/can/microchip,mpfs-can.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 Microchip PolarFire SoC (MPFS) can controller 11 - Conor Dooley <conor.dooley@microchip.com> 14 - $ref: can-controller.yaml# 18 const: microchip,mpfs-can 28 - description: AHB peripheral clock 29 - description: CAN bus clock [all …]
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/freebsd/sys/contrib/device-tree/Bindings/rtc/ |
H A D | microchip,mfps-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Microchip PolarFire Soc (MPFS) RTC 11 - $ref: rtc.yaml# 14 - Daire McNamara <daire.mcnamara@microchip.com> 15 - Lewis Hanly <lewis.hanly@microchip.com> 20 - microchip,mpfs-rtc 27 - description: | [all …]
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/freebsd/sys/contrib/device-tree/Bindings/spi/ |
H A D | microchip,mpfs-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 - Conor Dooley <conor.dooley@microchip.com> 19 - items: 20 - enum: 21 - microchip,mpfs-qspi 22 - microchip,pic64gx-qspi 23 - const: microchip,coreqspi-rtl-v2 [all …]
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/freebsd/sys/contrib/device-tree/Bindings/usb/ |
H A D | microchip,mpfs-musb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip MPFS USB Controller 10 - $ref: usb-drd.yaml# 13 - Conor Dooley <conor.dooley@microchip.com> 18 - microchip,mpfs-musb 29 interrupt-names: 31 - const: dma [all …]
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/freebsd/sys/contrib/device-tree/Bindings/gpio/ |
H A D | microchip,mpfs-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip MPFS GPIO Controller 10 - Conor Dooley <conor.dooley@microchip.com> 15 - enum: 16 - microchip,mpfs-gpio 17 - microchip,coregpio-rtl-v3 28 interrupt-controller: true [all …]
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/freebsd/sys/contrib/device-tree/Bindings/i2c/ |
H A D | microchip,corei2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip MPFS I2C Controller 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 - $ref: /schemas/i2c/i2c-controller.yaml# 18 - items: 19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs 20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core 21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core [all …]
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