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Searched +full:mpc8360 +full:- +full:gtm (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dfsl,gtm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/fsl,gtm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-purpose Timers Module
10 - J. Neuschäfer <j.ne@posteo.net>
16 - items:
17 - enum:
18 - fsl,mpc8308-gtm
19 - fsl,mpc8313-gtm
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H A Dfsl,gtm.txt1 * Freescale General-purpose Timers Module
4 - compatible : should be
5 "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
6 "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
7 "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
8 - reg : should contain gtm registers location and length (0x40).
9 - interrupts : should contain four interrupts.
10 - clock-frequency : specifies the frequency driving the timer.
15 compatible = "fsl,mpc8360-gtm", "fsl,gtm";
18 interrupt-parent = <&ipic>;
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc836x_rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2007-2008 MontaVista Software, Inc.
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
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H A Dmpc836x_mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <32768>; // L1, 32K
39 i-cache-size = <32768>; // L1, 32K
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - J. Neuschäfer <j.ne@posteo.net>
14 controlling chip-wide low-power states as well as peripheral clock gating.
20 For "fsl,mpc8349-pmc", sleep specifiers consist of one cell. For each bit that
25 For "fsl,mpc8536-pmc", sleep specifiers consist of three cells, the third of
27 resume. The first two cells are as described for fsl,mpc8548-pmc. This
31 For "fsl,mpc8548-pmc" or "fsl,mpc8641d-pmc", Sleep specifiers consist of one
33 into DEVDISR2, if present -- this cell should be zero or absent if the
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