Searched full:mout_audss (Results 1 – 4 of 4) sorted by relevance
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | samsung,s5pv210-audss-clock.yaml | 29 Optional fixed rate PLL reference clock, parent of mout_audss. If not
33 Input PLL to the AudioSS block, parent of mout_audss.
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| H A D | samsung,exynos-audss-clock.yaml | 31 Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
34 Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
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| /linux/drivers/clk/samsung/ |
| H A D | clk-s5pv210-audss.c | 113 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
118 mout_i2s_p[0] = "mout_audss"; in s5pv210_audss_clk_probe()
130 "dout_aud_bus", "mout_audss", 0, in s5pv210_audss_clk_probe()
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| H A D | clk-exynos-audss.c | 126 const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; in exynos_audss_clk_probe()
183 clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss", in exynos_audss_clk_probe()
200 "mout_audss", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
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